Re: [PATCH v3 12/15] arm64/mm: Split __flush_tlb_range() to elide trailing DSB

Jonathan Cameron
2023-12-14T16:45:50Z

On Thu, 14 Dec 2023 15:22:06 +0000
Jean-Philippe Brucker <jean-philippe@linaro.org> wrote:

> On Thu, Dec 14, 2023 at 12:30:55PM +0000, Robin Murphy wrote:
> > > Robin, Jean-Philippe -- do we need to make sure that the SMMU has completed
> > > its TLB invalidation before issuing an ATC invalidate? My half-baked worry
> > > is whether or not an ATS request could refill the ATC before the TLBI
> > > has completed, therefore rendering the ATC invalidation useless.
> >
> > I would agree, and the spec for CMD_ATC_INV does call out a
> > TLBI->sync->ATCI->sync sequence. At the moment the SVA notifier is issuing
> > its own command-based TLBIs anyway so the necessary sync is implicit there,
> > but if and when we get BTM support wired up properly it would be nice not to
> > have to bodge in an additional sync/DSB.
>
> Yes agreed, with BTM the CPU must call the notifier that issues ATC
> invalidation after completing the TLBI+DSB instructions.
>
> SMMU IHI0070F.a 3.9.1 ATS Interface
>
> Software must ensure that the SMMU TLB invalidation is complete before
> initiating the ATC invalidation.
>
> I'm guessing BTM will be enabled in the SMMU driver sometime soon, given
> that there already is one implementation in the wild that could use it. I
> think we didn't enable it because of the lack of separation between shared
> and private VMIDs, but that may now be solvable with the recent rework of
> the VMID allocator.
>

+CC Shameer. We'll indeed need to fix this when enabling BTM.

Thanks for the heads up.

Jonathan

> Thanks,
> Jean
>