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[209.85.220.65]) by mx.google.com with SMTPS id z22sor2709719ote.183.2019.06.08.13.00.43 for (Google Transport Security); Sat, 08 Jun 2019 13:00:43 -0700 (PDT) Received-SPF: pass (google.com: domain of martin.blumenstingl@googlemail.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@googlemail.com header.s=20161025 header.b=iCm+4VqZ; spf=pass (google.com: domain of martin.blumenstingl@googlemail.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=martin.blumenstingl@googlemail.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=googlemail.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=wvkpFaao1bpKQ1FWayC3EusodSIMGE6w694SSNfMEPA=; b=iCm+4VqZSt6kP2oAqKNK9ttO+n1BscayXijHYPF97LlKXKRTy/SQJZN8g6ptnB37GY 2qpvcyeM4ipaUGv65IBoJk02Qm02N2zjp1eUXMCq+AN4trMiVdYmCSqfFUNnpqCeLs73 Hp2SAEt7Mvr8wKtGNmb72g6Av+lQZbvcgd3MLPNKA40YmEdhRMR+1oBXTPPWTEwvlJzj tt/CdN305EsiUJ9JuqpVD3D7V7QibejrzDVzpZwMPG3HBT3xKfgfibme2CBG/1ZgwDvL bvRP90LTWNSXGucxuU1L5uvWJLtOO0uXdC4As8XsFXZ4rsoY6xw7ij12LQADBI9QEXzN hF4Q== X-Google-Smtp-Source: APXvYqzE1S4at/LKVQiJdPOZ7qR8leNmGzSuvzyjOZztdFT72UxQXxBOmWKetA1I5Vc/iv6tZY4wzFoHoG2nI91n1qA= X-Received: by 2002:a9d:6d8d:: with SMTP id x13mr23458026otp.6.1560024042878; Sat, 08 Jun 2019 13:00:42 -0700 (PDT) MIME-Version: 1.0 References: <20190321214401.GC19508@bombadil.infradead.org> <5cad2529-8776-687e-58d0-4fb9e2ec59b1@amlogic.com> <32799846-b8f0-758f-32eb-a9ce435e0b79@amlogic.com> <79b81748-8508-414f-c08a-c99cb4ae4b2a@amlogic.com> <8cb108ff-7a72-6db4-660d-33880fcee08a@amlogic.com> <45ce172c-5c76-bb69-31c8-af91e8ffdd68@amlogic.com> In-Reply-To: <45ce172c-5c76-bb69-31c8-af91e8ffdd68@amlogic.com> From: Martin Blumenstingl Date: Sat, 8 Jun 2019 22:00:31 +0200 Message-ID: Subject: Re: 32-bit Amlogic (ARM) SoC: kernel BUG in kfree() To: Liang Yang Cc: Matthew Wilcox , mhocko@suse.com, linux@armlinux.org.uk, linux-kernel@vger.kernel.org, rppt@linux.ibm.com, linux-mm@kvack.org, linux-mtd@lists.infradead.org, linux-amlogic@lists.infradead.org, akpm@linux-foundation.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="UTF-8" X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Hi Liang, On Thu, Apr 11, 2019 at 5:00 AM Liang Yang wrote: > > Hi Martin, > On 2019/4/11 1:54, Martin Blumenstingl wrote: > > Hi Liang, > > > > On Wed, Apr 10, 2019 at 1:08 PM Liang Yang wrote: > >> > >> Hi Martin, > >> > >> On 2019/4/5 12:30, Martin Blumenstingl wrote: > >>> Hi Liang, > >>> > >>> On Fri, Mar 29, 2019 at 8:44 AM Liang Yang wrote: > >>>> > >>>> Hi Martin, > >>>> > >>>> On 2019/3/29 2:03, Martin Blumenstingl wrote: > >>>>> Hi Liang, > >>>> [......] > >>>>>> I don't think it is caused by a different NAND type, but i have followed > >>>>>> the some test on my GXL platform. we can see the result from the > >>>>>> attachment. By the way, i don't find any information about this on meson > >>>>>> NFC datasheet, so i will ask our VLSI. > >>>>>> Martin, May you reproduce it with the new patch on meson8b platform ? I > >>>>>> need a more clear and easier compared log like gxl.txt. Thanks. > >>>>> your gxl.txt is great, finally I can also compare my own results with > >>>>> something that works for you! > >>>>> in my results (see attachment) the "DATA_IN [256 B, force 8-bit]" > >>>>> instructions result in a different info buffer output. > >>>>> does this make any sense to you? > >>>>> > >>>> I have asked our VLSI designer for explanation or simulation result by > >>>> an e-mail. Thanks. > >>> do you have any update on this? > >> Sorry. I haven't got reply from VLSI designer yet. We tried to improve > >> priority yesterday, but i still can't estimate the time. There is no > >> document or change list showing the difference between m8/b and gxl/axg > >> serial chips. Now it seems that we can't use command NFC_CMD_N2M on nand > >> initialization for m8/b chips and use *read byte from NFC fifo register* > >> instead. > > thank you for the status update! > > > > I am trying to understand your suggestion not to use NFC_CMD_N2M: > > the documentation (public S922X datasheet from Hardkernel: [0]) states > > that P_NAND_BUF (NFC_REG_BUF in the meson_nand driver) can hold up to > > four bytes of data. is this the "read byte from NFC FIFO register" you > > mentioned? > > > You are right.take the early meson NFC driver V2 on previous mail as a > reference. > > > Before I spend time changing the code to use the FIFO register I would > > like to wait for an answer from your VLSI designer. > > Setting the "correct" info buffer length for NFC_CMD_N2M on the 32-bit > > SoCs seems like an easier solution compared to switching to the FIFO > > register. Keeping NFC_CMD_N2M on the 32-bit SoCs also allows us to > > have only one code-path for 32 and 64 bit SoCs, meaning we don't have > > to maintain two separate code-paths for basically the same > > functionality (assuming that NFC_CMD_N2M is not completely broken on > > the 32-bit SoCs, we just don't know how to use it yet). > > > All right. I am also waiting for the answer. do you have any update on this? Martin