From: Anup Patel <apatel@ventanamicro.com>
To: Jesse Taube <jesse@rivosinc.com>
Cc: linux-riscv@lists.infradead.org,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
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"Arnaldo Carvalho de Melo" <acme@kernel.org>,
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"Shuah Khan" <shuah@kernel.org>,
"Himanshu Chauhan" <hchauhan@ventanamicro.com>,
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"Thomas Gleixner" <tglx@linutronix.de>,
"Thomas Weißschuh" <thomas.weissschuh@linutronix.de>,
"Vincenzo Frascino" <vincenzo.frascino@arm.com>,
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"Akihiko Odaki" <akihiko.odaki@daynix.com>,
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linux-kernel@vger.kernel.org, linux-mm@kvack.org,
linux-perf-users@vger.kernel.org,
linux-kselftest@vger.kernel.org
Subject: Re: [PATCH 5/8] riscv: hw_breakpoint: Use icount for single stepping
Date: Mon, 11 Aug 2025 15:11:27 +0530 [thread overview]
Message-ID: <CAK9=C2X2J4ROJ7nKB0hcD9dVav7ZMFWw2Qy+GEsmYN_Tt8DxPQ@mail.gmail.com> (raw)
In-Reply-To: <20250805193955.798277-6-jesse@rivosinc.com>
Hi Jesse,
On Wed, Aug 6, 2025 at 1:10 AM Jesse Taube <jesse@rivosinc.com> wrote:
>
> The Sdtrig RISC-V ISA extension does not have a resume flag for
> returning to and executing the instruction at the breakpoint.
> To avoid skipping the instruction or looping, it is necessary to remove
> the hardware breakpoint and single step. Use the icount feature of
> Sdtrig to accomplish this. Use icount as default with an option to allow
> software-based single stepping when hardware or SBI does not have
> icount functionality, as it may cause unwanted side effects when reading
> the instruction from memory.
>
> Signed-off-by: Jesse Taube <jesse@rivosinc.com>
> ---
> OpenSBI implementation of sbi_debug_read_triggers does not return the
> updated CSR values. There needs to be a check for working
> sbi_debug_read_triggers before this works.
>
> https://lists.riscv.org/g/tech-prs/message/1476
>
> RFC -> V1:
> - Add dbtr_mode to rv_init_icount_trigger
> - Add icount_triggered to check which breakpoint was triggered
> - Fix typo: s/affects/effects
> - Move HW_BREAKPOINT_COMPUTE_STEP to Platform type
> ---
> arch/riscv/Kconfig | 11 ++
> arch/riscv/kernel/hw_breakpoint.c | 179 +++++++++++++++++++++++++++---
> 2 files changed, 172 insertions(+), 18 deletions(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index fd8b62cdc6f5..37f01ed199f3 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -546,6 +546,17 @@ config RISCV_COMBO_SPINLOCKS
>
> endchoice
>
> +config HW_BREAKPOINT_COMPUTE_STEP
> + bool "Allow computing hardware breakpoint step address"
> + default n
> + depends on HAVE_HW_BREAKPOINT
> + help
> + Select this option if hardware breakpoints are desired, but
> + hardware or SBI does not have icount functionality. This may cause
> + unwanted side effects when reading the instruction from memory.
> +
> + If unsure, say N.
> +
We expect the same kernel image to work on a platform with
icount triggers and without icount triggers.
Please drop this kconfig option. The decision of falling back to
computing hardware breakpoint step address should be at
boot-time and not compile-time.
Regards,
Anup
next prev parent reply other threads:[~2025-08-11 9:41 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-05 19:39 [PATCH 0/8] riscv: add initial support for hardware breakpoints Jesse Taube
2025-08-05 19:39 ` [PATCH 1/8] riscv: Add insn.c, consolidate instruction decoding Jesse Taube
2025-08-05 19:39 ` [PATCH 2/8] riscv: Add SBI debug trigger extension and function ids Jesse Taube
2025-08-05 19:39 ` [PATCH 3/8] riscv: insn: Add get_insn_nofault Jesse Taube
2025-08-05 19:39 ` [PATCH 4/8] riscv: Introduce support for hardware break/watchpoints Jesse Taube
2025-08-05 19:39 ` [PATCH 5/8] riscv: hw_breakpoint: Use icount for single stepping Jesse Taube
2025-08-11 9:41 ` Anup Patel [this message]
2025-08-05 19:39 ` [PATCH 6/8] riscv: ptrace: Add hw breakpoint support Jesse Taube
2025-08-05 19:39 ` [PATCH 7/8] riscv: ptrace: Add hw breakpoint regset Jesse Taube
2025-08-05 19:39 ` [PATCH 8/8] selftests: riscv: Add test for hardware breakpoints Jesse Taube
-- strict thread matches above, loose matches on Subject: below --
2025-08-22 17:47 [PATCH 0/8] riscv: add initial support " Jesse Taube
2025-08-22 17:47 ` [PATCH 5/8] riscv: hw_breakpoint: Use icount for single stepping Jesse Taube
2025-08-26 4:38 ` Himanshu Chauhan
2025-08-27 8:04 ` Charlie Jenkins
2025-08-28 17:36 ` Jesse T
2025-08-28 17:46 ` Jesse T
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