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From: Andy Lutomirski <luto@kernel.org>
To: Dave Hansen <dave.hansen@intel.com>
Cc: Andy Lutomirski <luto@kernel.org>, X86 ML <x86@kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Borislav Petkov <bp@alien8.de>,
	Linus Torvalds <torvalds@linux-foundation.org>,
	Andrew Morton <akpm@linux-foundation.org>,
	Mel Gorman <mgorman@suse.de>,
	"linux-mm@kvack.org" <linux-mm@kvack.org>,
	Nadav Amit <nadav.amit@gmail.com>, Rik van Riel <riel@redhat.com>,
	Arjan van de Ven <arjan@linux.intel.com>,
	Peter Zijlstra <peterz@infradead.org>
Subject: Re: [PATCH v2 00/10] PCID and improved laziness
Date: Wed, 14 Jun 2017 15:48:09 -0700	[thread overview]
Message-ID: <CALCETrXT28SpE1SnYJNVOLadTaOKRYyQ2887BAU5S7X8YxS4ig@mail.gmail.com> (raw)
In-Reply-To: <6da4aea9-ef52-694d-9a03-285c32018326@intel.com>

On Wed, Jun 14, 2017 at 3:18 PM, Dave Hansen <dave.hansen@intel.com> wrote:
> On 06/13/2017 09:56 PM, Andy Lutomirski wrote:
>> 2. Mms that have been used recently on a given CPU might get to keep
>>    their TLB entries alive across process switches with this patch
>>    set.  TLB fills are pretty fast on modern CPUs, but they're even
>>    faster when they don't happen.
>
> Let's not forget that TLBs are also getting bigger.  The bigger TLBs
> help ensure that they *can* survive across another process's timeslice.
>
> Also, the cost to refill the paging structure caches is going up.  Just
> think of how many cachelines you have to pull in to populate a
> ~1500-entry TLB, even if the CPU hid the latency of those loads.

Then throw EPT into the mix for extra fun.  I wonder if we should try
to allocate page tables from nearby physical addresses if we think we
might be running as a guest.

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  reply	other threads:[~2017-06-14 22:48 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-14  4:56 [PATCH v2 00/10] PCID and improved laziness Andy Lutomirski
2017-06-14  4:56 ` [PATCH v2 01/10] x86/ldt: Simplify LDT switching logic Andy Lutomirski
2017-06-15 18:53   ` Rik van Riel
2017-06-14  4:56 ` [PATCH v2 02/10] x86/mm: Remove reset_lazy_tlbstate() Andy Lutomirski
2017-06-15 19:29   ` Rik van Riel
2017-06-14  4:56 ` [PATCH v2 03/10] x86/mm: Give each mm TLB flush generation a unique ID Andy Lutomirski
2017-06-14 15:54   ` Dave Hansen
2017-06-14 17:16     ` Andy Lutomirski
2017-06-14  4:56 ` [PATCH v2 04/10] x86/mm: Track the TLB's tlb_gen and update the flushing algorithm Andy Lutomirski
2017-06-14  4:56 ` [PATCH v2 05/10] x86/mm: Rework lazy TLB mode and TLB freshness tracking Andy Lutomirski
2017-06-14  6:09   ` Juergen Gross
2017-06-19 22:00     ` Andy Lutomirski
2017-06-14 22:33   ` Dave Hansen
2017-06-14 22:42     ` Andy Lutomirski
2017-06-18  8:06   ` Nadav Amit
2017-06-19 21:58     ` Andy Lutomirski
2017-06-14  4:56 ` [PATCH v2 06/10] x86/mm: Stop calling leave_mm() in idle code Andy Lutomirski
2017-06-14  4:56 ` [PATCH v2 07/10] x86/mm: Disable PCID on 32-bit kernels Andy Lutomirski
2017-06-14  4:56 ` [PATCH v2 08/10] x86/mm: Add nopcid to turn off PCID Andy Lutomirski
2017-06-14  4:56 ` [PATCH v2 09/10] x86/mm: Enable CR4.PCIDE on supported systems Andy Lutomirski
2017-06-14  5:30   ` Juergen Gross
2017-06-14  4:56 ` [PATCH v2 10/10] x86/mm: Try to preserve old TLB entries using PCID Andy Lutomirski
2017-06-18  6:26   ` Nadav Amit
2017-06-19 22:02     ` Andy Lutomirski
2017-06-19 22:53       ` Nadav Amit
2017-06-19 23:04         ` Nadav Amit
2017-06-14 22:18 ` [PATCH v2 00/10] PCID and improved laziness Dave Hansen
2017-06-14 22:48   ` Andy Lutomirski [this message]
     [not found]     ` <CA+55aFw_PYteXjaFZw0vkn4XgOomaqN3JWN-NDh_HdaN8Jb0ZA@mail.gmail.com>
     [not found]       ` <CA+55aFxzXmg3Kkk+NaXYFy4JsQpbUcZ+CGTgTqAdOsOGqA_E_Q@mail.gmail.com>
2017-06-14 22:58         ` Linus Torvalds
2017-06-18 21:29 ` Levin, Alexander (Sasha Levin)
2017-06-19  4:43   ` Andy Lutomirski

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