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Sun, 04 Oct 2026 23:39:03 -0700 (PDT) Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3901.100.1.1.12\)) Subject: Re: [PATCH 1/1] x86/mm: fix incomplete page-table invalidation with TCE From: Nadav Amit In-Reply-To: <20261005052302.43042-1-lance.yang@linux.dev> Date: Mon, 5 Oct 2026 09:38:47 +0300 Cc: dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@kernel.org, mingo@redhat.com, bp@alien8.de, x86@kernel.org, hpa@zytor.com, riel@surriel.com, linux-kernel@vger.kernel.org, qi.zheng@linux.dev, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, brendan.jackman@linux.dev, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Manali.Shukla@amd.com, mingo@kernel.org, stable@vger.kernel.org, toshi.kani@hpe.com, david@kernel.org, mikhail.v.gavrilov@gmail.com, pfalcato@suse.de Content-Transfer-Encoding: 7bit Message-Id: References: <20261005052302.43042-1-lance.yang@linux.dev> To: Lance Yang X-Mailer: Apple Mail (2.3901.100.1.1.12) X-Rspamd-Server: rspam05 X-Rspamd-Queue-Id: 90BF6C0003 X-Stat-Signature: d8go8b74pnckpxm6e89ficu9thgfnzpm X-Rspam-User: X-HE-Tag: 1791182345-977444 X-HE-Meta: U2FsdGVkX18wP9L+kiPkZ91WSL00+UwrZTy4pG1GpiMSzgFCp+KcTvHMBgiJjX1O5eIWr0DEZAMUMIM3HMqNMWmh/lP5ei1FLyqk9tGJKh7oNttYzQtxjLq6rH5+46a17RPS62AgxMaxCQhKNSdXjlcYcEUt6uHTjwurv0P9SxeG5le8LoHuXBlLUQd7rFcIxjIT7mSzwxPmY/nEa/QQvV+2ANsLMw+nWXzrl3K9PalQquEm1aFIrb8voKojrhSjVjqIf1Z/QWc4SKEf3b43qgQnmpqvgYxpBtudRliz3RA7kdUjU2f8PXOgWFSj38ynXIvZ350iEDhlb+B54ULqg++14vXiEV0QK46Zf86dcItcmsoWc8B6UeGz49nd9SH4G9vngK7vUY2v73j5RhXo/tWtGYFHTZzoqL5nFBY7ozJ3ioDJNhFi9RuTvKambMXiblgeDNWyCmg25Q3MIEDzLPMAIai4hwEOl0hPRt6+gV2aj12elqBywNOPbAUa4ZROju2fJLF3jWfC8CNCV87lInxxNG76WYdwjTy1onQk1UFS+pg4BlrmrAfMiomgr89mKcAgzPsIfckdDH3Jnw6WJauXeyATNZmCgtkTcPWKr4uHTuLnASQLiY5ddvl4Zawa5G52xs1ROHFFXK9ZBhbKr4fp0XB1jXcvrijFyPToLXnhfeTDDnOf24w4Exx+AstSxkrgJHqDXnWhNxOylyoaoTAi5LGf59EZR3vKZo6FF07p5IWUtgTOx5aWHE/jadukDMhuwGI2n+BBxqEZGZvYl8WxjnSgCcn6HXgosOpbT+qbcu1wAUgJjdOjWxVqk+OrrBJqMvfA9MRhta6Kg60rtQGtDQOvM2OrOYduVUIXxGVlaLmpK/KervqLkNknzg5EnfJNzVE8u1e3r9QKB5BowdiJ93MapE+8wm+iVWINvUXDbQNkSuc4QV0rsjmeSn5vrWlKxbc44ouXbUtULEJ FV0Le5t+ jmXLMSTSn4Uk4nDwTThnvRETdlk+vHvAl2yq4CNwYwNaAgoeuZpZrFmkdEUCm9qLr6qkKCKoJDo431SDWH+tF1s2vhbLtGzoqe1hFnMfPvtGkF5Il9QyvihzAIbSemQsr+AoWNDGz0yAQuX3AJYvohcPDxAPuwJS6myCpPWT0L3U6ndiex18vVIuXEPGtHTBP8XFvYFnAzK4k1fguMdv8UN5Oahb/gYz/mLc6bFAh4DdGmLw8n+1AcakXt1L+8I+sHL8j0OSmQ4jM04yxf42V+ZQeTSAFdE26x0o+iFBh6dmC19mMbGlWae8oQ3CVtPuScLfpQmy6U5kVS3UBdo4M6E4L7bcomCLlqoLhUFKJypORBamY2UP0JSxZU9kVh4ywTutPR6x40Iwa73VgvKDzCTw3IjN9CLs5OA/gu8lYH6IcwjPqFJwcVBRL+QV+PBW8hb4PmJFGPWW+qjVsN0ju2nfwzna81bBavDchWWXy0XRpsJ6RUckItcGQx9WC0qtfNE3U1+uAn7qA9TKMpV2t21rspA== Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: > > > On 5 Oct 2026, at 8:23, Lance Yang wrote: > > pud_free_pmd_page() uses a single-address invalidation to flush the > paging-structure caches before freeing the page tables. With AMD TCE > enabled, this only invalidates upper-level entries associated with the > target address. Cached PMD entries for other addresses in the PUD range can > still reference the PTE pages being freed. > > The AMD manual quoted in the commit enabling TCE says these instructions > remove > > "only those upper-level entries that lead to the target PTE in the page > table hierarchy, leaving unrelated upper-level entries intact." > > Even with all PTEs cleared, speculative page walks can cache present PMD > entries after the earlier TLB purge. > > Use a full TLB flush before freeing the page tables on CPUs with TCE. Keep > the single-address invalidation otherwise. > > Fixes: 440a65b7d25f ("x86/mm: Enable AMD translation cache extensions") > Cc: stable@vger.kernel.org > Signed-off-by: Lance Yang > --- > arch/x86/mm/pgtable.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c > index 4a105f283cfb..6b7fa44f1bf6 100644 > --- a/arch/x86/mm/pgtable.c > +++ b/arch/x86/mm/pgtable.c > @@ -727,7 +727,16 @@ int pud_free_pmd_page(pud_t *pud, unsigned long addr) > * via normal page walks. Make them unreachable > * in cached mid-level walks too: > */ > - flush_tlb_kernel_range(addr, addr + PAGE_SIZE-1); > + if (boot_cpu_has(X86_FEATURE_TCE)) { > + /* > + * With TCE enabled, a single-address flush does not invalidate > + * cached PMD entries for the rest of the PUD range. > + */ > + flush_tlb_all(); > + } else { > + /* INVLPG to clear all paging-structure caches */ > + flush_tlb_kernel_range(addr, addr + PAGE_SIZE-1); > + } > It might be cleaner to replace flush_tlb_all() with: flush_tlb_kernel_range(addr, addr + PUD_SIZE - 1); While the flush-ceiling would usually end up doing a full flush, the code would be easier to follow (the very least). Maybe adding stride to kernel TLB range flushing would make sense in the future.