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From: Michal Hocko <mhocko@suse.com>
To: "Huang, Ying" <ying.huang@intel.com>
Cc: Bharata B Rao <bharata@amd.com>,
	Aneesh Kumar K V <aneesh.kumar@linux.ibm.com>,
	linux-mm@kvack.org, linux-kernel@vger.kernel.org,
	Andrew Morton <akpm@linux-foundation.org>,
	Alistair Popple <apopple@nvidia.com>,
	Dan Williams <dan.j.williams@intel.com>,
	Dave Hansen <dave.hansen@intel.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	Hesham Almatary <hesham.almatary@huawei.com>,
	Jagdish Gediya <jvgediya.oss@gmail.com>,
	Johannes Weiner <hannes@cmpxchg.org>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Tim Chen <tim.c.chen@intel.com>, Wei Xu <weixugc@google.com>,
	Yang Shi <shy828301@gmail.com>
Subject: Re: [RFC] memory tiering: use small chunk size and more tiers
Date: Wed, 2 Nov 2022 09:17:38 +0100	[thread overview]
Message-ID: <Y2Inot4i4xUGH60O@dhcp22.suse.cz> (raw)
In-Reply-To: <87bkppbx75.fsf@yhuang6-desk2.ccr.corp.intel.com>

On Wed 02-11-22 16:02:54, Huang, Ying wrote:
> Michal Hocko <mhocko@suse.com> writes:
> 
> > On Wed 02-11-22 08:39:49, Huang, Ying wrote:
> >> Michal Hocko <mhocko@suse.com> writes:
> >> 
> >> > On Mon 31-10-22 09:33:49, Huang, Ying wrote:
> >> > [...]
> >> >> In the upstream implementation, 4 tiers are possible below DRAM.  That's
> >> >> enough for now.  But in the long run, it may be better to define more.
> >> >> 100 possible tiers below DRAM may be too extreme.
> >> >
> >> > I am just curious. Is any configurations with more than couple of tiers
> >> > even manageable? I mean applications have been struggling even with
> >> > regular NUMA systems for years and vast majority of them is largerly
> >> > NUMA unaware. How are they going to configure for a more complex system
> >> > when a) there is no resource access control so whatever you aim for
> >> > might not be available and b) in which situations there is going to be a
> >> > demand only for subset of tears (GPU memory?) ?
> >> 
> >> Sorry for confusing.  I think that there are only several (less than 10)
> >> tiers in a system in practice.  Yes, here, I suggested to define 100 (10
> >> in the later text) POSSIBLE tiers below DRAM.  My intention isn't to
> >> manage a system with tens memory tiers.  Instead, my intention is to
> >> avoid to put 2 memory types into one memory tier by accident via make
> >> the abstract distance range of each memory tier as small as possible.
> >> More possible memory tiers, smaller abstract distance range of each
> >> memory tier.
> >
> > TBH I do not really understand how tweaking ranges helps anything.
> > IIUC drivers are free to assign any abstract distance so they will clash
> > without any higher level coordination.
> 
> Yes.  That's possible.  Each memory tier corresponds to one abstract
> distance range.  The larger the range is, the higher the possibility of
> clashing is.  So I suggest to make the abstract distance range smaller
> to reduce the possibility of clashing.

I am sorry but I really do not understand how the size of the range
actually addresses a fundamental issue that each driver simply picks
what it wants. Is there any enumeration defining basic characteristic of
each tier? How does a driver developer knows which tear to assign its
driver to?

-- 
Michal Hocko
SUSE Labs


  reply	other threads:[~2022-11-02  8:17 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-27  6:59 [RFC] memory tiering: use small chunk size and more tiers Huang Ying
2022-10-27 10:45 ` Aneesh Kumar K V
2022-10-28  3:03   ` Huang, Ying
2022-10-28  5:05     ` Aneesh Kumar K V
2022-10-28  5:46       ` Huang, Ying
2022-10-28  8:04         ` Bharata B Rao
2022-10-28  8:33           ` Huang, Ying
2022-10-28 13:53             ` Bharata B Rao
2022-10-31  1:33               ` Huang, Ying
2022-11-01 14:34                 ` Michal Hocko
2022-11-02  0:39                   ` Huang, Ying
2022-11-02  7:51                     ` Michal Hocko
2022-11-02  8:02                       ` Huang, Ying
2022-11-02  8:17                         ` Michal Hocko [this message]
2022-11-02  8:28                           ` Huang, Ying
2022-11-02  8:39                             ` Michal Hocko
2022-11-02  8:45                               ` Huang, Ying

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