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[35.185.214.157]) by smtp.gmail.com with ESMTPSA id t14sm6393455pjl.10.2021.10.13.10.04.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Oct 2021 10:04:10 -0700 (PDT) Date: Wed, 13 Oct 2021 17:04:06 +0000 From: Sean Christopherson To: Brijesh Singh Cc: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-coco@lists.linux.dev, linux-mm@kvack.org, linux-crypto@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , Dov Murik , Tobin Feldman-Fitzthum , Borislav Petkov , Michael Roth , Vlastimil Babka , "Kirill A . Shutemov" , Andi Kleen , tony.luck@intel.com, marcorr@google.com, sathyanarayanan.kuppuswamy@linux.intel.com Subject: Re: [PATCH Part2 v5 37/45] KVM: SVM: Add support to handle MSR based Page State Change VMGEXIT Message-ID: References: <20210820155918.7518-1-brijesh.singh@amd.com> <20210820155918.7518-38-brijesh.singh@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Rspamd-Server: rspam01 X-Rspamd-Queue-Id: 69F1110000A5 X-Stat-Signature: jno8dysibj47ut1jcyz8o3d64s3fcx8m Authentication-Results: imf12.hostedemail.com; dkim=pass header.d=google.com header.s=20210112 header.b=iyi+jmtE; dmarc=pass (policy=reject) header.from=google.com; spf=pass (imf12.hostedemail.com: domain of seanjc@google.com designates 209.85.215.175 as permitted sender) smtp.mailfrom=seanjc@google.com X-HE-Tag: 1634144652-511849 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Tue, Oct 12, 2021, Sean Christopherson wrote: > If we are unable to root cause and fix the bug, I think a viable workaround would > be to clear the hardware present bit in unrelated SPTEs, but keep the SPTEs > themselves. The idea mostly the same as the ZAPPED_PRIVATE concept from the initial > TDX RFC. MMU notifier invalidations, memslot removal, RMP restoration, etc... would > all continue to work since the SPTEs is still there, and KVM's page fault handler > could audit any "blocked" SPTE when it's refaulted (I'm pretty sure it'd be > impossible for the PFN to change, since any PFN change would require a memslot > update or mmu_notifier invalidation). > > The downside to that approach is that it would require walking all SPTEs to do a > memslot deletion, i.e. we'd lose the "fast zap" behavior. If that's a performance > issue, the behavior could be opt-in (but not for SNP/TDX). Another option if we introduce private memslots is to preserve private memslots on unrelated deletions. The argument being that (a) private memslots are a new feature so there's no prior uABI to break, and (b) if not zapping private memslot SPTEs in response to the guest remapping a BAR somehow breaks GPU pass-through, then the bug is all but guaranteed to be somewhere besides KVM's memslot logic.