Re: [PATCH v2 1/4] kernel/resource: Introduce managed SOFT RESERVED resources

Li Zhijian
2025-03-10T05:52:46Z

>On Fri, Mar 07, 2025 at 05:56:25AM +0000, Zhijian Li (Fujitsu) wrote:
>> Hello Fontenot,
>>
>> I hope this email finds you well.
>>
>> Thank you very much for this patch. We've encountered the same issue in our product,
>> and your patch works.
>>
>> We do hope this issue will be resolved in the upstream kernel soon.
>>
>
>snip
>
>>
>>
>> I noticed your earlier discussions about designing a new approach to solve this problem,
>> which I'm pretty excited about. Do you have any idea when you might post the updated
>> version? We'd love to help out with reviewing and testing..
>>
>> If you run into any roadblocks and need a hand, just let us know. we'd be delighted to help.
>>
>> As far as I know, this issue usually arises on Real CXL machines, but for ease of testing
>> and validation, we modified QEMU to simulate the intersection of 'Soft Reserved' and
>> the CXL region, which would aid in verification.
>
>Hi Zhijian,
>
>Wow - I want that! Can you share that QEMU branch? With QEMU cmdline too.
>

Hi Terry and Alison

Well, it's a simple hack within the QEMU and seabios project. Their
modifications are as below:

Note: the QEMU's modification exposed the CFMWs region instead of the CXL
memory region(that the Real CXL machine did)

After the guest started, you could see the iomem tree:

a90000000-1a8fffffff : CXL Window 0
a90000000-1a8fffffff : Soft Reserved

QEMU:
=====================
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index f199a8c7ad19..484ad7e5e632 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -963,6 +963,9 @@ void pc_memory_init(PCMachineState *pcms,
memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw,
"cxl-fixed-memory-region", fw->size);
memory_region_add_subregion(system_memory, fw->base, &fw->mr);
+#define E820_TYPE_SOFT_RESERVED 0xefffffff
+ /* add special purpose memory */
+ e820_add_entry(fw->mr.addr, fw->mr.size , E820_TYPE_SOFT_RESERVED);
cxl_fmw_base += fw->size;
cxl_resv_end = cxl_fmw_base;
}

seabios
=====================
diff --git a/src/e820map.c b/src/e820map.c
index c761e5e98a75..9440039541a6 100644
--- a/src/e820map.c
+++ b/src/e820map.c
@@ -54,6 +54,7 @@ e820_type_name(u32 type)
case E820_ACPI: return "ACPI";
case E820_NVS: return "NVS";
case E820_UNUSABLE: return "UNUSABLE";
+ case E820_TYPE_SOFT_RESERVED: return "Soft Reserved";
default: return "UNKNOWN";
}
}
diff --git a/src/e820map.h b/src/e820map.h
index 07ce16ec213f..dd416d5ba3df 100644
--- a/src/e820map.h
+++ b/src/e820map.h
@@ -8,6 +8,7 @@
#define E820_ACPI 3
#define E820_NVS 4
#define E820_UNUSABLE 5
+#define E820_TYPE_SOFT_RESERVED 0xefffffff

struct e820entry {
u64 start;
diff --git a/src/fw/paravirt.c b/src/fw/paravirt.c
index e5d4eca0cb5a..38a9bfed04df 100644
--- a/src/fw/paravirt.c
+++ b/src/fw/paravirt.c
@@ -781,6 +781,12 @@ static int qemu_early_e820(void)
if (RamSizeOver4G < table.address + table.length - 0x100000000LL)
RamSizeOver4G = table.address + table.length - 0x100000000LL;
}
+ break;
+ case E820_TYPE_SOFT_RESERVED:
+ e820_add(table.address, table.length, table.type);
+ dprintf(1, "qemu/e820: addr 0x%016llx len 0x%016llx [Sort reserved]\n",
+ table.address, table.length);
+ break;
}
}

====================
QEMU comand line(nothing special to QEMU expect specifying your own bios):

/path/to/qemu <...args...> \
-machine type=q35,cxl=on \
-bios /path/to/seabios/out/bios.bin \
-nographic \
-object memory-backend-ram,id=vmem0,share=on,size=4G \
-device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \
-device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 \
-device cxl-type3,bus=root_port13,volatile-memdev=vmem0,id=cxl-vmem0 \
-M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=64G