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bh=905lAPt08QRFR8FR2phEdH/qr4W7W6RJu2a1XAXvmfQ=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=qVA4bpKb7d2JG/KjhM8G/2/iPPdIAuE33rZ8yiPVZXPBVehBvfAeQFqDTgH9WobjD Ss9Ca7uAZL+f6RZvebjoxsozRItTQb0nx1PZzlPwfgqPWkZrwwJcJuPnnvKDRCcweR a+QoyiQHknBUjuaxV5v5n1UjMGvl51GmqDsO/j/Ow8n4/0dF8XerHrkcS7yUx9lS2B acP+z4IYMHF8Dvix/Mk8pOK8eLZMQuUxoSs2m26pHjbyoI6/whwfJxSAbbnbSYqRr3 3+rmJXmyU8wKMtxT8DdJdNSRCLTlF0EFofWuJh/ndpNOi1G34B6W15OItFlMsxONde jWG+49VqKLV2Q== Date: Wed, 15 Mar 2023 11:49:15 +0200 From: Mike Rapoport To: "Matthew Wilcox (Oracle)" Cc: linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, Catalin Marinas , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v4 09/36] arm64: Implement the new page table range API Message-ID: References: <20230315051444.3229621-1-willy@infradead.org> <20230315051444.3229621-10-willy@infradead.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230315051444.3229621-10-willy@infradead.org> X-Rspamd-Queue-Id: C32A114000F X-Stat-Signature: f6e5rp5pujuiacioh5hi63xduotwte71 X-Rspam-User: X-Rspamd-Server: rspam08 X-HE-Tag: 1678873769-578742 X-HE-Meta: U2FsdGVkX1+HHeQiI8TGYlCfpuRSZ76+JIBj2ezOx81/dG1AJrjo/U6BXp+WP2y7fw/Uk2vHX9wVQ1ymZZAHmgPQam6g9oWNe0pdI0b3MrA38PBEDADDOsPELozBjrzTUAMJibeVo/TxNAlx/WL7NgsCOpPPP2bbfFEJciiM+VhAio/DQyRj0tGpk/AV5PZ/4+WH65FgM8LTyO87cdrMX0/a+7jQb1gTHg8B5v7i8WZNIr5yF8zz2z7u1ADN8aS973xYpwyQHQnSzApk1a3GZn7rheGECs0+D6VcgzuI9ha8C42yfgvUISI6fAGiq01x7lwGYZRiu0we10PCOsdQZ4CGUZkIQidQaodrynEXR0j7fUF7QLi2BG0X09sR0v409yeejrDc+xeYSlXpck9kMMibjwtWwrEFZ+ZrkOJ/UqYKnf+OrB7UozAC02EylWmh74oxr9n7OpfJDrZpOpwboA1HQe0aXnZT1nl265Uv20UMDO/sxtw/I0GlLB0SCwYiqQTpxX5AGoC9/hwG/WMFKuJ4mG9K7jPWsGqx9zH1VEAiK32Mo5reXW0mzXX11uDakbTkU4vKmrsqNV6jtqc91FGQGGO8tASWOp1fdJg6B7kQhxpK1gKoe2WTjxIl21zHa66MDBcFbbH7VYV5FFMGEcngtUEF4vsT+JiIPYrS5X4EVRuZIA3UQFTJatAXuvFZCwo1FXtqoM6ZrNb8jwlVa9pBd/GZuyCe68K2M6dVl+RA6D4+5CZiSrJwf5GurdAi308jI9SZqj/myZ86DoP5xjpXMw9e6RfTeDqZU/8iHItWdJyJ+OsFbFiGaMJ59erzyW3ekwbsD0t7OOpJloyLtLoO/kob8NcM5ik+2+qYyXNw5WmT7xqDKFORUTeYmCw/3POJ4DoeKSKKzTDyppmdhW0DnxD0R7OIXdQzCM3oTdwCFYWZxxUVWMMdguXkMlFQlj5KsTOU1yqofnTUTUF sMZ2iTio cqzupZjFeXMObsygK8TaeN6k+jZFLk9RHSaMAwjqPoPgw7ERjgOG26BEl9K1qFzbvBQvcIwo4rglsFQZEzyF3ZUNUeXftYRcFyVxw32nPl7YaHG1pWBDVW69bb4Ylu3V3TVqpwbTZZBRVxiDvZGjGr+SOLIGiWVhW2NUwpWrbtb1785U7vQQnNWTm/1Yk/s45coWlcNPr1z1aLLCUwZwLRBdxTuv4Hr2rLDHTIYFrk3d3fXDK+uuF70I3QVPMHp9ubZ/a8wwvKNWDY+2Qfqff2TAGEjpQPIlCYiW9PRQt2vlET/YqBTXCwXRwVpVnPWVVMEXEzVpRJwEKlqJfcIqMkLH0/nWdoz1oq+cl5g6AKUoAFNbAwjPAjsqZfMQqEnLEsKNxh/QaEqwMYsXjlUcjIFeQmVCi7jZlbl+9satDUyoT9ffANUPuXXafoV9Jdm0Qo/Cg29K7twVpCpK0fy6IX7/nQNMZVTRLmjbwCif3LO84Rwg= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Wed, Mar 15, 2023 at 05:14:17AM +0000, Matthew Wilcox (Oracle) wrote: > Add set_ptes(), update_mmu_cache_range() and flush_dcache_folio(). > Change the PG_dcache_clean flag from being per-page to per-folio. > > Signed-off-by: Matthew Wilcox (Oracle) > Reviewed-by: Catalin Marinas > Cc: linux-arm-kernel@lists.infradead.org Acked-by: Mike Rapoport (IBM) > --- > arch/arm64/include/asm/cacheflush.h | 4 +++- > arch/arm64/include/asm/pgtable.h | 25 ++++++++++++++------ > arch/arm64/mm/flush.c | 36 +++++++++++------------------ > 3 files changed, 35 insertions(+), 30 deletions(-) > > diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h > index 37185e978aeb..d115451ed263 100644 > --- a/arch/arm64/include/asm/cacheflush.h > +++ b/arch/arm64/include/asm/cacheflush.h > @@ -114,7 +114,7 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *, > #define copy_to_user_page copy_to_user_page > > /* > - * flush_dcache_page is used when the kernel has written to the page > + * flush_dcache_folio is used when the kernel has written to the page > * cache page at virtual address page->virtual. > * > * If this page isn't mapped (ie, page_mapping == NULL), or it might > @@ -127,6 +127,8 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *, > */ > #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 > extern void flush_dcache_page(struct page *); > +void flush_dcache_folio(struct folio *); > +#define flush_dcache_folio flush_dcache_folio > > static __always_inline void icache_inval_all_pou(void) > { > diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h > index 9428748f4691..6fd012663a01 100644 > --- a/arch/arm64/include/asm/pgtable.h > +++ b/arch/arm64/include/asm/pgtable.h > @@ -355,12 +355,21 @@ static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, > set_pte(ptep, pte); > } > > -static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, > - pte_t *ptep, pte_t pte) > -{ > - page_table_check_ptes_set(mm, addr, ptep, pte, 1); > - return __set_pte_at(mm, addr, ptep, pte); > +static inline void set_ptes(struct mm_struct *mm, unsigned long addr, > + pte_t *ptep, pte_t pte, unsigned int nr) > +{ > + page_table_check_ptes_set(mm, addr, ptep, pte, nr); > + > + for (;;) { > + __set_pte_at(mm, addr, ptep, pte); > + if (--nr == 0) > + break; > + ptep++; > + addr += PAGE_SIZE; > + pte_val(pte) += PAGE_SIZE; > + } > } > +#define set_ptes set_ptes > > /* > * Huge pte definitions. > @@ -1059,8 +1068,8 @@ static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio) > /* > * On AArch64, the cache coherency is handled via the set_pte_at() function. > */ > -static inline void update_mmu_cache(struct vm_area_struct *vma, > - unsigned long addr, pte_t *ptep) > +static inline void update_mmu_cache_range(struct vm_area_struct *vma, > + unsigned long addr, pte_t *ptep, unsigned int nr) > { > /* > * We don't do anything here, so there's a very small chance of > @@ -1069,6 +1078,8 @@ static inline void update_mmu_cache(struct vm_area_struct *vma, > */ > } > > +#define update_mmu_cache(vma, addr, ptep) \ > + update_mmu_cache_range(vma, addr, ptep, 1) > #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) > > #ifdef CONFIG_ARM64_PA_BITS_52 > diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c > index 5f9379b3c8c8..deb781af0a3a 100644 > --- a/arch/arm64/mm/flush.c > +++ b/arch/arm64/mm/flush.c > @@ -50,20 +50,13 @@ void copy_to_user_page(struct vm_area_struct *vma, struct page *page, > > void __sync_icache_dcache(pte_t pte) > { > - struct page *page = pte_page(pte); > + struct folio *folio = page_folio(pte_page(pte)); > > - /* > - * HugeTLB pages are always fully mapped, so only setting head page's > - * PG_dcache_clean flag is enough. > - */ > - if (PageHuge(page)) > - page = compound_head(page); > - > - if (!test_bit(PG_dcache_clean, &page->flags)) { > - sync_icache_aliases((unsigned long)page_address(page), > - (unsigned long)page_address(page) + > - page_size(page)); > - set_bit(PG_dcache_clean, &page->flags); > + if (!test_bit(PG_dcache_clean, &folio->flags)) { > + sync_icache_aliases((unsigned long)folio_address(folio), > + (unsigned long)folio_address(folio) + > + folio_size(folio)); > + set_bit(PG_dcache_clean, &folio->flags); > } > } > EXPORT_SYMBOL_GPL(__sync_icache_dcache); > @@ -73,17 +66,16 @@ EXPORT_SYMBOL_GPL(__sync_icache_dcache); > * it as dirty for later flushing when mapped in user space (if executable, > * see __sync_icache_dcache). > */ > -void flush_dcache_page(struct page *page) > +void flush_dcache_folio(struct folio *folio) > { > - /* > - * HugeTLB pages are always fully mapped and only head page will be > - * set PG_dcache_clean (see comments in __sync_icache_dcache()). > - */ > - if (PageHuge(page)) > - page = compound_head(page); > + if (test_bit(PG_dcache_clean, &folio->flags)) > + clear_bit(PG_dcache_clean, &folio->flags); > +} > +EXPORT_SYMBOL(flush_dcache_folio); > > - if (test_bit(PG_dcache_clean, &page->flags)) > - clear_bit(PG_dcache_clean, &page->flags); > +void flush_dcache_page(struct page *page) > +{ > + flush_dcache_folio(page_folio(page)); > } > EXPORT_SYMBOL(flush_dcache_page); > > -- > 2.39.2 > > -- Sincerely yours, Mike.