Re: Excessive TLB flush ranges

Thomas Gleixner
2023-05-19T11:49:58Z

On Wed, May 17 2023 at 15:57, Nadav Amit wrote:
>> On May 17, 2023, at 3:31 AM, Thomas Gleixner <tglx@linutronix.de> wrote:
>> Maybe ARM[64] could do this smarter, but that would require to rewrite a
>> lot of code I assume.
>
> What you say makes sense - and I actually see that flush_tlb_page_nosync()
> needs a memory barrier.
>
> I just encountered recent patches that did the flushing on ARM in an
> async manner as I described. That is the reason I assumed it is more efficient.
>
> https://lore.kernel.org/linux-mm/20230410134352.4519-3-yangyicong@huawei.com/

This operates on a mm and is related to batched removal of user space
mappings.

That could be done for vmalloc too, but the life time tracking,
i.e. ensuring that a nosync flush has seen the final barrier which
ensures that the mapping is not longer visible might be slightly more
tricky. Especially with the full x86 centric code there.

Thanks,

tglx