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charset=us-ascii Content-Disposition: inline In-Reply-To: <20240403234054.2020347-8-debug@rivosinc.com> X-Rspam-User: X-Rspamd-Server: rspam02 X-Rspamd-Queue-Id: DA6C340015 X-Stat-Signature: bthwjmtp6jyaw4j9wj4jh8jpbtfhumeg X-HE-Tag: 1715381518-518622 X-HE-Meta: U2FsdGVkX1966ga+tPU5MLGVHV9zzARPCq4iTJJ4TkC/mQ6Z3lhtZybRdns3o9zZfM4eSDTqRIPIRfVS1t/B05RNZq8+UosbPcXnbPgsXsnLVDAY638NzSpKJwuobKKJLhWnZ6vSfnhYBK1UenWSB3sWPyhZamK4PivL0DXX/gbA2+2Pj5oApYbos+iz0uP7BR90Hkb+F2arZPDUT7AnJPJfO4/Bko1cU052GaqtfHA0UT11hPX0Ok2YU2J5b8HJOGlMPx6ew6Jv5PwiIS9zYeW9j47EWGKOm5BVY04ohud0VgGZyzD5gWG2BYCgkZDM3YRAnTg21nf9w/EAt79vYCrCu1yTw4MgFbP0SYvDFomsRdrYAFfd9/9AWkbXLy2wC2eaPB1Sq7X51NLhAluwN96B0M1cT0Q/FKJCvK7FFrA1hDw9gyUYUaXdQhyRcHHdLnNjXPZfzSMgiSahah1BBJ6vDqhsCA+xMrgUnFDzL9+/FjueVv5jHEhho8bZIrrxCHPZbJ+7nX0PSTS3mNc4dwevLr85+St27vQNrRnKF3cj0eqNPSCtYI1uq1Lbv7BmU5OvqV2l1no3SrTpqsoj/qfd47akj51SgzBSVdurjTl+UY6CysFWnSGQ/lx0hllBHpaQsh4ovpHoIv3q1SwvCNwDvWarhsHEJo2lF3WS7SaBmsDeTMiJpfNUe6Yf3PpSwxtW+NN+zAECtZFqjX8z/j3fMMNkyVpNMlUxM9JBHRCDFY8DWJtC0dC7ysxa9fsxP+IGHu+ZzSHPXmKJ/EQ0eR2QIW/i+SGKXTGYIyssbi1R/1UJPBuTFnCETSjS/6knxPyRiLT4bt81wb9n2Wd4bLiaqdCrVlFsf9gjNaehpqQwRpUstocqzozAr0mmbcs4wxk6Bf07YaQnFNtka3hzbYDqlGyE7uD8s6z9IgKddypX1MpqKkncPqx5yTvmxOHBYCcmrEGmzGC5TKx5GGv 5v03Nlny +iFltcM1XK0g0t7kg+Rc6DDcrXsq+0jo3cRtwlG0z1L8XgOfOnL9TlKoGWT8eTQvFb4ytNBsg/bIVrpFZJ3fuqATi5ZsN/Ff4HjQO60fky02Fk3GYN1sUOs0yRyxgYdOQkMygsZtC8ax7Xhlhr/CVTI2GVQ+Pm8TTvvEeV4YlrvVn8Lms/p/x5/1FsS/Sqy5baY1kL79k6a4lI48AsPZe8f2tAbynCYIXxM403XYlY8thNSyTcmFFGf9M2y/O7pHdmO8Z4aV+6FXbiUwhX4l167NRCgsjDokoagvhX4zDyvBDyHvgkSSdnMX7JdHRf5BnFBph808gFefwztwr21lZsjMze3CzTAbak5wiRF+H7ttTuZ5gALqZuDOXqjg6+xPKI3B04XsnX+qbf9X65ySdNktRFHemL9Y6i0Hjk+gYypCAGsu5pJnveUB9B2ZMKws6GCa5Q5upEn+JSmCu1jbYc9Hle+AGgODnEsFXpEtK1F9jLT8yaKPL6f0C+li01FbbkZ6eQXkuA2xOALPYXH/h7LvcKFASczYauyqGI+h38rBAa0kaH/QqSvL7/VIZfZuKXFaHu2k42rDc/qs= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Wed, Apr 03, 2024 at 04:34:55PM -0700, Deepak Gupta wrote: > Carves out space in arch specific thread struct for cfi status and shadow > stack in usermode on riscv. > > This patch does following > - defines a new structure cfi_status with status bit for cfi feature > - defines shadow stack pointer, base and size in cfi_status structure > - defines offsets to new member fields in thread in asm-offsets.c > - Saves and restore shadow stack pointer on trap entry (U --> S) and exit > (S --> U) > > Shadow stack save/restore is gated on feature availiblity and implemented > using alternative. CSR can be context switched in `switch_to` as well but > soon as kernel shadow stack support gets rolled in, shadow stack pointer > will need to be switched at trap entry/exit point (much like `sp`). It can > be argued that kernel using shadow stack deployment scenario may not be as > prevalant as user mode using this feature. But even if there is some > minimal deployment of kernel shadow stack, that means that it needs to be > supported. And thus save/restore of shadow stack pointer in entry.S instead > of in `switch_to.h`. > > Signed-off-by: Deepak Gupta > --- > arch/riscv/include/asm/processor.h | 1 + > arch/riscv/include/asm/thread_info.h | 3 +++ > arch/riscv/include/asm/usercfi.h | 24 ++++++++++++++++++++++++ > arch/riscv/kernel/asm-offsets.c | 4 ++++ > arch/riscv/kernel/entry.S | 26 ++++++++++++++++++++++++++ > 5 files changed, 58 insertions(+) > create mode 100644 arch/riscv/include/asm/usercfi.h > > diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h > index 6c5b3d928b12..f8decf357804 100644 > --- a/arch/riscv/include/asm/processor.h > +++ b/arch/riscv/include/asm/processor.h > @@ -14,6 +14,7 @@ > > #include > #include > +#include > > #ifdef CONFIG_64BIT > #define DEFAULT_MAP_WINDOW (UL(1) << (MMAP_VA_BITS - 1)) > diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/thread_info.h > index a503bdc2f6dd..f1dee307806e 100644 > --- a/arch/riscv/include/asm/thread_info.h > +++ b/arch/riscv/include/asm/thread_info.h > @@ -57,6 +57,9 @@ struct thread_info { > int cpu; > unsigned long syscall_work; /* SYSCALL_WORK_ flags */ > unsigned long envcfg; > +#ifdef CONFIG_RISCV_USER_CFI > + struct cfi_status user_cfi_state; > +#endif > #ifdef CONFIG_SHADOW_CALL_STACK > void *scs_base; > void *scs_sp; > diff --git a/arch/riscv/include/asm/usercfi.h b/arch/riscv/include/asm/usercfi.h > new file mode 100644 > index 000000000000..4fa201b4fc4e > --- /dev/null > +++ b/arch/riscv/include/asm/usercfi.h > @@ -0,0 +1,24 @@ > +/* SPDX-License-Identifier: GPL-2.0 > + * Copyright (C) 2024 Rivos, Inc. > + * Deepak Gupta > + */ > +#ifndef _ASM_RISCV_USERCFI_H > +#define _ASM_RISCV_USERCFI_H > + > +#ifndef __ASSEMBLY__ > +#include > + > +#ifdef CONFIG_RISCV_USER_CFI > +struct cfi_status { > + unsigned long ubcfi_en : 1; /* Enable for backward cfi. */ > + unsigned long rsvd : ((sizeof(unsigned long)*8) - 1); > + unsigned long user_shdw_stk; /* Current user shadow stack pointer */ > + unsigned long shdw_stk_base; /* Base address of shadow stack */ > + unsigned long shdw_stk_size; /* size of shadow stack */ > +}; > + > +#endif /* CONFIG_RISCV_USER_CFI */ > + > +#endif /* __ASSEMBLY__ */ > + > +#endif /* _ASM_RISCV_USERCFI_H */ > diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c > index a03129f40c46..5c5ea015c776 100644 > --- a/arch/riscv/kernel/asm-offsets.c > +++ b/arch/riscv/kernel/asm-offsets.c > @@ -44,6 +44,10 @@ void asm_offsets(void) > #endif > > OFFSET(TASK_TI_CPU_NUM, task_struct, thread_info.cpu); > +#ifdef CONFIG_RISCV_USER_CFI > + OFFSET(TASK_TI_CFI_STATUS, task_struct, thread_info.user_cfi_state); > + OFFSET(TASK_TI_USER_SSP, task_struct, thread_info.user_cfi_state.user_shdw_stk); > +#endif > OFFSET(TASK_THREAD_F0, task_struct, thread.fstate.f[0]); > OFFSET(TASK_THREAD_F1, task_struct, thread.fstate.f[1]); > OFFSET(TASK_THREAD_F2, task_struct, thread.fstate.f[2]); > diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S > index 9d1a305d5508..7245a0ea25c1 100644 > --- a/arch/riscv/kernel/entry.S > +++ b/arch/riscv/kernel/entry.S > @@ -60,6 +60,20 @@ SYM_CODE_START(handle_exception) > > REG_L s0, TASK_TI_USER_SP(tp) > csrrc s1, CSR_STATUS, t0 > + /* > + * If previous mode was U, capture shadow stack pointer and save it away > + * Zero CSR_SSP at the same time for sanitization. > + */ > + ALTERNATIVE("nop; nop; nop; nop", > + __stringify( \ > + andi s2, s1, SR_SPP; \ > + bnez s2, skip_ssp_save; \ > + csrrw s2, CSR_SSP, x0; \ > + REG_S s2, TASK_TI_USER_SSP(tp); \ > + skip_ssp_save:), > + 0, > + RISCV_ISA_EXT_ZICFISS, > + CONFIG_RISCV_USER_CFI) > csrr s2, CSR_EPC > csrr s3, CSR_TVAL > csrr s4, CSR_CAUSE > @@ -141,6 +155,18 @@ SYM_CODE_START_NOALIGN(ret_from_exception) > * structures again. > */ > csrw CSR_SCRATCH, tp > + > + /* > + * Going back to U mode, restore shadow stack pointer > + */ > + ALTERNATIVE("nop; nop", > + __stringify( \ > + REG_L s3, TASK_TI_USER_SSP(tp); \ > + csrw CSR_SSP, s3), > + 0, > + RISCV_ISA_EXT_ZICFISS, > + CONFIG_RISCV_USER_CFI) > + > 1: > #ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE > move a0, sp > -- > 2.43.2 > Reviewed-by: Charlie Jenkins