From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB9BEC25B10 for ; Mon, 13 May 2024 18:31:32 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 27C966B020B; Mon, 13 May 2024 14:31:32 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 202DC6B020D; Mon, 13 May 2024 14:31:32 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 017796B020E; Mon, 13 May 2024 14:31:31 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0010.hostedemail.com [216.40.44.10]) by kanga.kvack.org (Postfix) with ESMTP id DA3156B020B for ; Mon, 13 May 2024 14:31:31 -0400 (EDT) Received: from smtpin13.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay09.hostedemail.com (Postfix) with ESMTP id 7FF74809A0 for ; Mon, 13 May 2024 18:31:31 +0000 (UTC) X-FDA: 82114215582.13.1D7AC6C Received: from mail-pf1-f177.google.com (mail-pf1-f177.google.com [209.85.210.177]) by imf23.hostedemail.com (Postfix) with ESMTP id 9A5DC140026 for ; Mon, 13 May 2024 18:31:29 +0000 (UTC) Authentication-Results: imf23.hostedemail.com; dkim=pass header.d=rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=NcmpdnGf; spf=pass (imf23.hostedemail.com: domain of debug@rivosinc.com designates 209.85.210.177 as permitted sender) smtp.mailfrom=debug@rivosinc.com; dmarc=none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1715625089; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=9lfxB6TGC4fu8lY9DVlJ3Uo04rJaZ2CFPzF6bJyMTII=; b=a0iWGc5xP+/ix9ImDM6OUTxJ5EFhhuymf6FvOHjs7VQg504RJaDIv+KKXBksL1tO8yYs0z aHc/uxbkKSVMYV8+9K3qsEBaLv9OmnH10xvEOlyt1uRxET/AUbvg65QGDQK4fNDci54mo+ HdRV/06OtbMXkGizJaIG3gn3G2jh28E= ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1715625089; a=rsa-sha256; cv=none; b=bzWcLNeF/4vJjdNU6hRbmgNK6q3kA8RYSc90O02T8dntnVSIr2FZY2nb2brE/n3JTCAPNP v4g4wggjpOrS5DV4FvPmUP6mqT8GMRpTNLdeiNSQ5nebqH2AGLI6Tbyua64MWfkOR2+ouM ae+/IBkzR2ek8Sx7SYqRpYGvt6eLomA= ARC-Authentication-Results: i=1; imf23.hostedemail.com; dkim=pass header.d=rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=NcmpdnGf; spf=pass (imf23.hostedemail.com: domain of debug@rivosinc.com designates 209.85.210.177 as permitted sender) smtp.mailfrom=debug@rivosinc.com; dmarc=none Received: by mail-pf1-f177.google.com with SMTP id d2e1a72fcca58-6f44b390d5fso4020213b3a.3 for ; Mon, 13 May 2024 11:31:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1715625088; x=1716229888; darn=kvack.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=9lfxB6TGC4fu8lY9DVlJ3Uo04rJaZ2CFPzF6bJyMTII=; b=NcmpdnGf4YQQ69UzNzoseVOfbtpx+sJtduX4hYNnaG520O9mmlJC6cH+uB/wnR9qTc /MC8/0IvxMW+TAA2/gpfz98sk2ELyvoOhX0fb/oFuseAMF4RLAUAal+d22AvEIa0jo/j MNeiezPIPF5qB54KfunsFPJ/wrik7FGLhJOkDD6Wr+hw1Rp/erPotSaZc/3UxKNcsPpr Xj8tpXYD1iwk33GrH4Ot3LOhDOT4w1sOpJ0lOfk9us21sIffTIT8zUJCCuekeWXZVSzP vVXjZRu4YIYtNhxYyXgkWsTnKIYiPdVSmVrvZm65AxNwbLCPiJjDWxOxdRYCa69vUHr1 phdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715625088; x=1716229888; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=9lfxB6TGC4fu8lY9DVlJ3Uo04rJaZ2CFPzF6bJyMTII=; b=hDwcQfvbqVb+kgzYiE1EUCrdjP6P9uJcVao9Y/at6y8J02kQvkrtbCSyb+0UQImz48 vZaVC0ZYKqJs82ynfYdFnpnGE4X8rt4sD1OIv7aurAgRRvGekG+Qqgjg6yCH3MtxV8MI Tl3L/c+O0S4M6a9xwuSVrjfbzSa0eeqY6ky48Qd0xtf6rC8VmC0AyytXtH2YEBY9QldE Dl42QdgEIxQjdmNqhTXU+E973xmA3wJfCIxGPJ9Q+IGQba3B/anzXSuK+jNGBnxEdk59 RPRFbDxAn2nLdvw55Rdlh3ykkXdfrp8jqR2PgBieuFQ6VKLg6XAvC+OdNPB4oOgoVN66 LSMg== X-Forwarded-Encrypted: i=1; AJvYcCX98c1ZImoxrlrzp2xPdiR1coVomYAYzhSP3yTKhJzCuvWqh4SUHllHV12b+lOgf0IBMJpYq468IlutiApJivnieiM= X-Gm-Message-State: AOJu0Yz+3X7K32kQIzDl2FKSxYuwiYl1oeS++ZIalmiXLi469+mnRkli E+2iKNnNtwel34XHWZ5bQz0UiCVSY+FYBLJCRRoaCYuY52VgmJqoTBGm7fkZtJM= X-Google-Smtp-Source: AGHT+IH1OSRQPwx8UUxBA+2NIldqGQBfyQNuOaQuzBWIoDTXDv4FJlctQ5Ean61dJ4G8ZeTtENbZeA== X-Received: by 2002:a05:6a20:8428:b0:1a9:d9bb:acdc with SMTP id adf61e73a8af0-1afde10df02mr12897298637.28.1715625088408; Mon, 13 May 2024 11:31:28 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-6340b48a152sm8067572a12.20.2024.05.13.11.31.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 11:31:28 -0700 (PDT) Date: Mon, 13 May 2024 11:31:23 -0700 From: Deepak Gupta To: Charlie Jenkins Cc: paul.walmsley@sifive.com, rick.p.edgecombe@intel.com, broonie@kernel.org, Szabolcs.Nagy@arm.com, kito.cheng@sifive.com, keescook@chromium.org, ajones@ventanamicro.com, conor.dooley@microchip.com, cleger@rivosinc.com, atishp@atishpatra.org, alex@ghiti.fr, bjorn@rivosinc.com, alexghiti@rivosinc.com, samuel.holland@sifive.com, conor@kernel.org, linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-kselftest@vger.kernel.org, corbet@lwn.net, palmer@dabbelt.com, aou@eecs.berkeley.edu, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, oleg@redhat.com, akpm@linux-foundation.org, arnd@arndb.de, ebiederm@xmission.com, Liam.Howlett@oracle.com, vbabka@suse.cz, lstoakes@gmail.com, shuah@kernel.org, brauner@kernel.org, andy.chiu@sifive.com, jerry.shih@sifive.com, hankuan.chen@sifive.com, greentime.hu@sifive.com, evan@rivosinc.com, xiao.w.wang@intel.com, apatel@ventanamicro.com, mchitale@ventanamicro.com, dbarboza@ventanamicro.com, sameo@rivosinc.com, shikemeng@huaweicloud.com, willy@infradead.org, vincent.chen@sifive.com, guoren@kernel.org, samitolvanen@google.com, songshuaishuai@tinylab.org, gerg@kernel.org, heiko@sntech.de, bhe@redhat.com, jeeheng.sia@starfivetech.com, cyy@cyyself.name, maskray@google.com, ancientmodern4@gmail.com, mathis.salmen@matsal.de, cuiyunhui@bytedance.com, bgray@linux.ibm.com, mpe@ellerman.id.au, baruch@tkos.co.il, alx@kernel.org, david@redhat.com, catalin.marinas@arm.com, revest@chromium.org, josh@joshtriplett.org, shr@devkernel.io, deller@gmx.de, omosnace@redhat.com, ojeda@kernel.org, jhubbard@nvidia.com Subject: Re: [PATCH v3 17/29] prctl: arch-agnostic prctl for indirect branch tracking Message-ID: References: <20240403234054.2020347-1-debug@rivosinc.com> <20240403234054.2020347-18-debug@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: X-Rspamd-Server: rspam03 X-Rspamd-Queue-Id: 9A5DC140026 X-Rspam-User: X-Stat-Signature: 44qu4drsxxdo34f7d4ujgkz44f6fpsqo X-HE-Tag: 1715625089-408067 X-HE-Meta: U2FsdGVkX1/gDjCsxiRThzA4f9xX8jjcHDrxuTQJBWeHiZAtSPgjt1FoJWKvCyevyjja8b7ED6jvCsLx3JI775NOT46TVJojiwnA0/vmPbli5jkCwRV2aMggV3xcvcM31RYYee0zOoNyU99SGGvOW+rBlA17/tR8BkI6oSpD4IJ2hsD8dva9P/TdGfBgaViasUHxXMb9yKSZb+ijq7aK6ZS4GyKRkVTcc+HtjF4U1u5OisXo8H3gHpwoqIv+b7Chlzdq6/SwipUXZpsb44sjR4jXVYVwxKbxWwc+OnOU4KktZjetbY5jBJtT32vZXUSoJNVcRkP7Pv6av0KPr6n7IiJc1xvHpHwZGFrm2FDBkflNwLThP+bJkoY305yneyvzBErVlIOQ6iIfqDI2Ugsrnic/E5q5Lz3ziRkXy7VDgdP4dVy1MwHooAe5J/XuWPBRqkIwuCzQj0Tcyq4p1QlgHsupeDzCIrClVyiFNvynvtvNRHFZ5Xxr0QO/CtATBIUHwtZKjdDqU/xrsrHqvOr4efIwUW5yjGyeD6ybHjWEvQ4JACPZdbU5el2cK42fR/Aa3IQ3Lp95+u8mbPEIiUOJLxPIk2HVbTJ/MNy0NzQICXTvvhmPU2OGmdV4Umt0bBYgZyHS856kbNreX8XVEeU3v88a+KDJUCCU3A7q05aDNtQtpCzMf0OMm/2Zb+0DBsOtBHNqMd9Vi1XM4OdRIZ6cfjlRDli2nYsWUumKPEeg3t63tBic/0rnXXvPytzIfex+WFqtKTAgTb4FMN7plMBD5lXo9PIPQf+ARnGDu3RvsXdwDbB+4J3mYRxfyXRuNc0Zqbsoyk++ApLEyxDGKzWo71pExvNEfGSqTH9dDr91ozNg4P1tDDW3+H32M+jgAvCK0JAZEZZxo4QebLqh61YHuBFciNkEkIu6Vkmwy8WNzbO+AddumU78mwENZhbt/RNSSkvoqmX7AiOss6PkIKC 3SuWYF2T h2SGy9kpZjyOFGWnZVljmIMXVsDa6bIhmKc+4R4ItSSvHpXVzRfILsBHc5ZiES8eoDRusQEApbE9lZvw0d7XCscfOxZBGCx40IeyVAxSCI2YyHizc2y/LKFG4iQ7XYnulUbHidBhy0TVTYV335m/RxTi3CgY2KuMAOUTpFxgRyE0HDsgcgKWkr44/txlfz5d4aDYAItIB7Fn5FGP+hwPfr3sshZlx3vJywPogkxRpmPJl8fZesSzNZah1jJuAa9F3T4LE/XrBNKlmS9zx3H97p0mr0NyppNnCFehDDCsHu8KUOvOPt+HcvHVuyxrM/8jq4wDBfcmFmSNDVBij86Nv5Bmp1f0EdrHLBHGr1HxgkO65OjmuT0V05mmOb2Kccqmroxir6jkvtbVxdC24BkxzYJKhoIhvLcq+trFYh3PjJwZyl9GLpTZtdnW+qgS7roKukttPkSJmhSYISaBjwYEHF1ioU4kkHz4GFnQ7YwpifCXt0n1dQO6wcVjKbqGPlLgll/+J+UdlpkBXSo+qvGS9z9ExIH5HQS38+vdw X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Fri, May 10, 2024 at 04:29:19PM -0700, Charlie Jenkins wrote: >On Wed, Apr 03, 2024 at 04:35:05PM -0700, Deepak Gupta wrote: >> Three architectures (x86, aarch64, riscv) have support for indirect branch >> tracking feature in a very similar fashion. On a very high level, indirect >> branch tracking is a CPU feature where CPU tracks branches which uses >> memory operand to perform control transfer in program. As part of this >> tracking on indirect branches, CPU goes in a state where it expects a >> landing pad instr on target and if not found then CPU raises some fault >> (architecture dependent) >> >> x86 landing pad instr - `ENDBRANCH` >> aarch64 landing pad instr - `BTI` >> riscv landing instr - `lpad` >> >> Given that three major arches have support for indirect branch tracking, >> This patch makes `prctl` for indirect branch tracking arch agnostic. >> >> To allow userspace to enable this feature for itself, following prtcls are >> defined: >> - PR_GET_INDIR_BR_LP_STATUS: Gets current configured status for indirect >> branch tracking. >> - PR_SET_INDIR_BR_LP_STATUS: Sets a configuration for indirect branch >> tracking. >> Following status options are allowed >> - PR_INDIR_BR_LP_ENABLE: Enables indirect branch tracking on user >> thread. >> - PR_INDIR_BR_LP_DISABLE; Disables indirect branch tracking on user >> thread. >> - PR_LOCK_INDIR_BR_LP_STATUS: Locks configured status for indirect branch >> tracking for user thread. >> >> Signed-off-by: Deepak Gupta >> --- >> include/uapi/linux/prctl.h | 27 +++++++++++++++++++++++++++ >> kernel/sys.c | 30 ++++++++++++++++++++++++++++++ >> 2 files changed, 57 insertions(+) >> >> diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h >> index 3c66ed8f46d8..b7a8212a068e 100644 >> --- a/include/uapi/linux/prctl.h >> +++ b/include/uapi/linux/prctl.h >> @@ -328,4 +328,31 @@ struct prctl_mm_map { >> */ >> #define PR_LOCK_SHADOW_STACK_STATUS 73 >> >> +/* >> + * Get the current indirect branch tracking configuration for the current >> + * thread, this will be the value configured via PR_SET_INDIR_BR_LP_STATUS. >> + */ >> +#define PR_GET_INDIR_BR_LP_STATUS 74 >> + >> +/* >> + * Set the indirect branch tracking configuration. PR_INDIR_BR_LP_ENABLE will >> + * enable cpu feature for user thread, to track all indirect branches and ensure >> + * they land on arch defined landing pad instruction. >> + * x86 - If enabled, an indirect branch must land on `ENDBRANCH` instruction. >> + * arch64 - If enabled, an indirect branch must land on `BTI` instruction. >> + * riscv - If enabled, an indirect branch must land on `lpad` instruction. >> + * PR_INDIR_BR_LP_DISABLE will disable feature for user thread and indirect >> + * branches will no more be tracked by cpu to land on arch defined landing pad >> + * instruction. >> + */ >> +#define PR_SET_INDIR_BR_LP_STATUS 75 >> +# define PR_INDIR_BR_LP_ENABLE (1UL << 0) >> + >> +/* >> + * Prevent further changes to the specified indirect branch tracking >> + * configuration. All bits may be locked via this call, including >> + * undefined bits. >> + */ >> +#define PR_LOCK_INDIR_BR_LP_STATUS 76 >> + >> #endif /* _LINUX_PRCTL_H */ >> diff --git a/kernel/sys.c b/kernel/sys.c >> index 242e9f147791..c770060c3f06 100644 >> --- a/kernel/sys.c >> +++ b/kernel/sys.c >> @@ -2330,6 +2330,21 @@ int __weak arch_lock_shadow_stack_status(struct task_struct *t, unsigned long st >> return -EINVAL; >> } >> >> +int __weak arch_get_indir_br_lp_status(struct task_struct *t, unsigned long __user *status) >> +{ >> + return -EINVAL; >> +} >> + >> +int __weak arch_set_indir_br_lp_status(struct task_struct *t, unsigned long __user *status) >> +{ >> + return -EINVAL; >> +} >> + >> +int __weak arch_lock_indir_br_lp_status(struct task_struct *t, unsigned long __user *status) >> +{ >> + return -EINVAL; >> +} >> + > >These weak references each cause a warning: > >kernel/sys.c:2333:12: warning: no previous prototype for 'arch_get_indir_br_lp_status' [-Wmissing-prototypes] > 2333 | int __weak arch_get_indir_br_lp_status(struct task_struct *t, unsigned long __user *status) > | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ >kernel/sys.c:2338:12: warning: no previous prototype for 'arch_set_indir_br_lp_status' [-Wmissing-prototypes] > 2338 | int __weak arch_set_indir_br_lp_status(struct task_struct *t, unsigned long __user *status) > | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ >kernel/sys.c:2343:12: warning: no previous prototype for 'arch_lock_indir_br_lp_status' [-Wmissing-prototypes] > 2343 | int __weak arch_lock_indir_br_lp_status(struct task_struct *t, unsigned long __user *status) > >Can the definitions be added to include/linux/mm.h alongside the >*_shadow_stack_status() definitions? Noted. Will work on a fix for this. > >- Charlie > >> #define PR_IO_FLUSHER (PF_MEMALLOC_NOIO | PF_LOCAL_THROTTLE) >> >> #ifdef CONFIG_ANON_VMA_NAME >> @@ -2787,6 +2802,21 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, arg2, unsigned long, arg3, >> return -EINVAL; >> error = arch_lock_shadow_stack_status(me, arg2); >> break; >> + case PR_GET_INDIR_BR_LP_STATUS: >> + if (arg3 || arg4 || arg5) >> + return -EINVAL; >> + error = arch_get_indir_br_lp_status(me, (unsigned long __user *) arg2); >> + break; >> + case PR_SET_INDIR_BR_LP_STATUS: >> + if (arg3 || arg4 || arg5) >> + return -EINVAL; >> + error = arch_set_indir_br_lp_status(me, (unsigned long __user *) arg2); >> + break; >> + case PR_LOCK_INDIR_BR_LP_STATUS: >> + if (arg3 || arg4 || arg5) >> + return -EINVAL; >> + error = arch_lock_indir_br_lp_status(me, (unsigned long __user *) arg2); >> + break; >> default: >> error = -EINVAL; >> break; >> -- >> 2.43.2 >>