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[34.142.255.199]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-842828e228asm22864909b3a.47.2026.06.09.03.45.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2026 03:45:47 -0700 (PDT) Date: Tue, 9 Jun 2026 10:45:39 +0000 From: Pranjal Shrivastava To: David Matlack Cc: kexec@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-pci@vger.kernel.org, Adithya Jayachandran , Alexander Graf , Alex Williamson , Bjorn Helgaas , Chris Li , David Rientjes , Jacob Pan , Jason Gunthorpe , Jonathan Corbet , Josh Hilke , Leon Romanovsky , Lukas Wunner , Mike Rapoport , Parav Pandit , Pasha Tatashin , Pratyush Yadav , Saeed Mahameed , Samiullah Khawaja , Shuah Khan , Vipin Sharma , William Tu , Yi Liu Subject: Re: [PATCH v6 01/12] PCI: liveupdate: Set up FLB handler for the PCI core Message-ID: References: <20260522202410.3104264-1-dmatlack@google.com> <20260522202410.3104264-2-dmatlack@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Rspamd-Server: rspam04 X-Rspamd-Queue-Id: 2B5B9100011 X-Stat-Signature: q5fjzxdbxq3najc3azx1t9me59nsz6ay X-Rspam-User: X-HE-Tag: 1781001949-233541 X-HE-Meta: U2FsdGVkX1/mVTL4UiU9iupKLRqatgUkAripLLOyTj6GStno6SjCIL9VCXaOS7YwfVoGudrHM3URJsZK/eLQuk4/1qDuQRX4AldWueuZGgGRusWsgMBpCv43oudZtmOAQdyY5b9czt+hBSVRdBQfBDCUUgPYnDWZnAnxT+82/AnYK6o2bHFhFWR8kQo0/nJ8NXmdYNLl+HR+/1jS4WYivd2VuR0xP3L4FHybZkSuDp53NEc0TMw1uuw92Ub9cQFEGuJtVsHiZn5VOm1j9b/kKXVq01CrVFE24bAdnKE8XXyCxL3Y3TJet7IoU4za5zTJf/7VbNb8eY0KNLy/48I+PS5/Ydy1HxzVvzwdCUOmEaGmXV2ZmfHYJsOUcrm+SJJvebVXvwrJl8WVPrzsEL/vCZnUioxcM+BzvaXQBDS2gleRjt/bx7xDllqBGe+rbZCOg3Cl03O2gTE2soFxbJ4nSj5/GUh9w2YdWj4iEOx3FnsDDkvLDHEgDHaMmznfqxKVOBuCo23Gb8Oo3cLfoyHrM0NJcxlCWSDn7klLtdY5r5JzvqhRRBKHusglttSTT6rJmPvTtpOCMT8nl4PsmxYJybyZRSyCv5W+McltjEiAvK18v09mXRzdvTtEx+DU2s9ArLUGnbEgn51tjOdYLxe1dbMlfEMzHJlcCcIzCq1E9h4rz997WoclUVfNATNxPX6ue1EK7WKid/mQYgPHtzRMjtrWHSg2kZnF+5SK48XmYFsyptDCtJhTj133JVh/3dqVwy/gFC4h+ZibIOcE1AaTeypZF+fMTvlfCg55MHa5d9DBhGamWU1L+lTWqpcpEdb1/+4RkTsWkA9im541ctOWVFQoSCf41SKt7Njzx9NcAiQQcwpg6UdWymWzvkq82fJjCe5BDyWFOOz4/iHo+HH0NiA4jOUh93XXi97HnYfRVUVCDxepELvbIF1HAmNd0KAML8aK82AW7t4y1Gzyse8 fkaeAEmm g0SrmtBkurlNYVHZd1TDcD8Df2QzDRdK08wdJDqGQjeIqyb5UwNKZawHjGSTg+JVEkncAtJsHn3hj0VvIwIvMMkSWOeYm8Z+Mv2JICLGKejvpcy4XSaskdT2CpYtmVRRJvlG0e+ZfJ0zf3RY7ERB1QdwKbfl77T2O/xbTuApBh83E507zGin7pObzgKeuzvpMZPTMrP/vGgsb9qfUoQTYYf5FRirCf3wb0M+xXb5Xik88HSpb7vDKp4/ea2DrCX6l5duoRP69w7tb9K2nI9Ev2CySyfEayCOAZGC005FHQYqbemztfom6Py8+VfvmSI3hHv4r1D6zKUr4GWphGp2645MDkxqOE3vrer5IEzLiQgsabwc= Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Mon, Jun 08, 2026 at 08:51:00PM +0000, David Matlack wrote: > On 2026-06-05 05:41 AM, Pranjal Shrivastava wrote: > > On Fri, May 22, 2026 at 08:23:59PM +0000, David Matlack wrote: > > > Set up a File-Lifecycle-Bound (FLB) handler for the PCI core to enable > > > it to participate in the preservation of PCI devices across Live Update. > > > Essentially, this commit enables the PCI core to allocate a struct > > > (struct pci_ser) and preserve it across a Live Update whenever at least > > > one device is preserved. > > > > > > Preserving PCI devices across Live Update is built on top of the Live > > > Update Orchestrator's (LUO) support for file preservation. Drivers are > > > expected to expose a file to userspace to represent a single PCI device > > > and support preservation of that file. This is intended primarily to > > > support preservation of PCI devices bound to VFIO drivers. > > > [...] > > > + * struct pci_ser - PCI Subsystem Live Update State > > > + * > > > + * This struct tracks state about all devices that are being preserved across > > > + * a Live Update for the next kernel. > > > + * > > > + * @max_nr_devices: The length of the devices[] flexible array. > > > + * @nr_devices: The number of devices that were preserved. > > > + * @devices: Flexible array of pci_dev_ser structs for each device. > > > + */ > > > +struct pci_ser { > > > + u32 max_nr_devices; > > > + u32 nr_devices; > > > + struct pci_dev_ser devices[]; > > > +} __packed; > > > + > > > +/* Ensure all elements of devices[] are naturally aligned. */ > > > +static_assert(offsetof(struct pci_ser, devices) % sizeof(unsigned long) == 0); > > > +static_assert(sizeof(struct pci_dev_ser) % sizeof(unsigned long) == 0); > > > > Minor Nit: Shall we consider using specific bitwidth types here? > > I'm wondering if down the line another u32 field is added to > > struct pci_dev_ser.. in that case on a 32-bit machine 12 % 4 == 0 but on > > a 64-bit machine 12 % 8 != 0.. > > I think natural alignment is what matters for efficient access of the > array elements. So failing the assert only on 64-bit architectures seems > like the correct behavior. > Ack. I guess what I was trying to say was we'd anyway need to keep both architectures in mind, i.e. adding members should be 64-bit aligned (which implicitly also handles 32-bit) as with the current assert any new addition would have to be both 32 & 64-bit aligned. I guess we can keep this as is. Thanks, Praan