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[91.12.104.251]) by smtp.gmail.com with ESMTPSA id l4-20020a05600c1d0400b003db0ad636d1sm15217382wms.28.2023.02.27.09.01.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 Feb 2023 09:01:02 -0800 (PST) Message-ID: Date: Mon, 27 Feb 2023 18:01:00 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.2 Subject: Re: [PATCH mm-unstable v1 11/26] microblaze/mm: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE To: Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, Andrew Morton , Hugh Dickins , John Hubbard , Jason Gunthorpe , Mike Rapoport , Yang Shi , Vlastimil Babka , Nadav Amit , Andrea Arcangeli , Peter Xu , linux-mm@kvack.org, x86@kernel.org, linux-alpha@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, linux-ia64@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@lists.linux-m68k.org, linux-mips@vger.kernel.org, openrisc@lists.librecores.org, linux-parisc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-um@lists.infradead.org, linux-xtensa@linux-xtensa.org, Michal Simek References: <20230113171026.582290-1-david@redhat.com> <20230113171026.582290-12-david@redhat.com> <9ed766a6-cf06-535d-3337-ea6ff25c2362@redhat.com> From: David Hildenbrand Organization: Red Hat In-Reply-To: X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Rspam-User: X-Rspamd-Server: rspam02 X-Rspamd-Queue-Id: AE1774001D X-Stat-Signature: p3h6buu5nfbshrod86fjqhgu4skkmrw1 X-HE-Tag: 1677517273-835832 X-HE-Meta: U2FsdGVkX1+OoYBM+2NfE9rqWn340r1qwnM7GpOXhmL8yWD5+rZoUC0Ax0weW7qR/KjwlqAbHlxrDwEfFIqzjiYu43QuMT1cO8GU/V3Xfm8+Xu05i/lq1V2fDk8ywDyXdW3hfbXhTeV/lcttXNtUYaU515aLK/vAGaz6h0lGmptg5YSGAB4e9Y697+FKroA1aqyfBYRYntt0VRuPzVcpoMZoykfJX/3i+srqODJoe3hLsio/u/xk/ZPrNhzE9E1soNKhOvfaI3ViCLjLQcoxdpOMYzVJS9cyUwmvWQuL4e2BkWfTpn2UqUxRHqSIDLXqWf0VXGFeGoxyN6XDL7+wQJ8dIeGSQClIrtfy7pEVJRsUTfYHpzTKm8S852cW704jq3360B3DUfA5NNtvSYM0i8YuA3nInfVSoCSXrGluroeBDQx0gVTctjSFs0ky30QOsYbggWpeCuppkspRogrgPNx2gPpdFoShq5YUS1U/h4wzOvXr8MJZs3g6V7lek8Vg1aHvxwf3l01ThO91dTPQKm8BnbKhopebp9N/7UXJK4qnM4YFtNglg3ejqs6n71k36SM2bwri8mj5+zMI0j6hpi+2Rjjax6ZX4IXfG2wyHVDQ1MoUXT92+Y5VUh6BUCYEBe8JMOe6Ydz4ASU2m1j/RRdfasuLUFMFKT7pUf0ZVB/4uOAiLyPS6Cw85i/rV3xwQv1e39MU5qh+XhC33JDKibW7rUtmA+SmtsxrS6PV1Nl8cC4IpA/eg54y+/dmEZTEyt2BJCcChdy+E61KDuQ1sXmObmBwUNU1Lqy1y2QtCxrf6iTbnaa+ZrJn7AYhVtf4buoKnSnNM+LPFYINSZO0ghzYzLAjdTyTWLDCoGy+lY4R4/9j94lZquxCaNbROUrG6YLH1OfSuZqttbYCW502D1hM0H/FeQRFPU8z+CWC8C0u/wxGAAeoV9Vhm1xd5TI46Ccs/wr7xKJjWWl9St0 nKzfi00r QaV60hPnrJiQYA8Iy3ydr4n7RyHxiVcx8CiRmUXYGCwQOW0MLg+2LmZ+USsHqASxcHpJ+0beJDgEDvifVUmvYm/rXSDhctJVyH+Q2xtpj6eMqwu7HN94+fYgDmaZ6GDRWgHT8WZBXrDhcAG7Rxd2Vwt3T37ZiHM91kFLKBO4vjokYSgrA2FtppWqVFPJbc1rXWH+5rrupC9xIYZYHkrzJ9QA7wUPjrWj6ecB807bPESVXPOH3Mz2Xg9yyD1XxaTTeOjacrRHgqa6+u1rX3rjSquxJa/EJpG4bM2GLbNRPCXUL5hVU63QCAzom0AnX/2pov9Bqara6+i0rNjhQIdsnQZT/3D6oa8DRovwz+Mq+vjNWseYbz6RdNw9xDKvoopu0dfccWqzV7ehbHvylOErEFOkmVCsPE3rr5p93 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: >>>> /* >>>> * Externally used page protection values. >>>> diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h >>>> index 42f5988e998b..7e3de54bf426 100644 >>>> --- a/arch/microblaze/include/asm/pgtable.h >>>> +++ b/arch/microblaze/include/asm/pgtable.h >>>> @@ -131,10 +131,10 @@ extern pte_t *va_to_pte(unsigned long address); >>>> * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB >>>> * miss handler. Bit 27 is PAGE_USER, thus selecting the correct >>>> * zone. >>>> - * - PRESENT *must* be in the bottom two bits because swap cache >>>> - * entries use the top 30 bits. Because 4xx doesn't support SMP >>>> - * anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30 >>>> - * is cleared in the TLB miss handler before the TLB entry is loaded. >>>> + * - PRESENT *must* be in the bottom two bits because swap PTEs use the top >>>> + * 30 bits. Because 4xx doesn't support SMP anyway, M is irrelevant so we >>>> + * borrow it for PAGE_PRESENT. Bit 30 is cleared in the TLB miss handler >>>> + * before the TLB entry is loaded. >>> >>> So the PowerPC 4xx comment is still here? >> >> I only dropped the comment above __swp_type(). I guess you mean that we >> could also drop the "Because 4xx doesn't support SMP anyway, M is >> irrelevant so we borrow it for PAGE_PRESENT." sentence, correct? Not > > Yes, that's what I meant. > >> sure about the "Bit 30 is cleared in the TLB miss handler" comment, if >> that can similarly be dropped. > > No idea, didn't check. But if it was copied from PPC, chances are > high it's no longer true.... I'll have a look. > >>>> * - All other bits of the PTE are loaded into TLBLO without >>>> * * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for >>>> * software PTE bits. We actually use bits 21, 24, 25, and >>>> @@ -155,6 +155,9 @@ extern pte_t *va_to_pte(unsigned long address); >>>> #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */ >>>> #define _PMD_PRESENT PAGE_MASK >>>> >>>> +/* We borrow bit 24 to store the exclusive marker in swap PTEs. */ >>>> +#define _PAGE_SWP_EXCLUSIVE _PAGE_DIRTY >>> >>> _PAGE_DIRTY is 0x80, so this is also bit 7, thus the new comment is >>> wrong? >> >> In the example, I use MSB-0 bit numbering (which I determined to be >> correct in microblaze context eventually, but I got confused a couple a >> times because it's very inconsistent). That should be MSB-0 bit 24. > > Thanks, TIL microblaze uses IBM bit numbering... I assume IBM bit numbering corresponds to MSB-0 bit numbering, correct? I recall that I used the comment above "/* Definitions for MicroBlaze. */" as an orientation. 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RPN..................... 0 0 EX WR ZSEL....... W I M G So ... either we adjust both or we leave it as is. (again, depends on what the right thing to to is -- which I don't know :) ) -- Thanks, David / dhildenb