From: Dave Hansen <dave.hansen@intel.com>
To: Vignesh Balasubramanian <vigbalas@amd.com>,
linux-kernel@vger.kernel.org, linux-toolchains@vger.kernel.org
Cc: mpe@ellerman.id.au, npiggin@gmail.com,
christophe.leroy@csgroup.eu, aneesh.kumar@kernel.org,
naveen.n.rao@linux.ibm.com, ebiederm@xmission.com,
keescook@chromium.org, x86@kernel.org,
linuxppc-dev@lists.ozlabs.org, linux-mm@kvack.org,
bpetkov@amd.com, jinisusan.george@amd.com, matz@suse.de,
binutils@sourceware.org, jhb@FreeBSD.org,
felix.willgerodt@intel.com
Subject: Re: [PATCH 1/1] x86/elf: Add a new .note section containing Xfeatures information to x86 core files
Date: Thu, 14 Mar 2024 08:37:09 -0700 [thread overview]
Message-ID: <dd54d6de-0bcc-4b2e-a420-b1a429b06246@intel.com> (raw)
In-Reply-To: <20240314112359.50713-2-vigbalas@amd.com>
On 3/14/24 04:23, Vignesh Balasubramanian wrote:
> Add a new .note section containing type, size, offset and flags of
> every xfeature that is present.
Mechanically, I'd much rather have all of that info in the cover letter
in the actual changelog instead.
I'd also love to see a practical example of what an actual example core
dump looks like on two conflicting systems:
* Total XSAVE size
* XCR0 value
* XSTATE_BV from the core dump
* XFEATURE offsets for each feature
Do you have any information about what other OSes are doing in this
area? I thought Windows, for instance, was even less flexible about the
XSAVE format than Linux is.
Why didn't LWP cause this problem?
From the cover letter:
> But this patch series depends on heuristics based on the total XSAVE
> register set size and the XCR0 mask to infer the layouts of the
> various register blocks for core dumps, and hence, is not a foolproof
> mechanism to determine the layout of the XSAVE area.
It may not be theoretically foolproof. But I'm struggling to think of a
case where it would matter in practice. Is there any CPU from any
vendor where this is actually _needed_?
Sure, it's ugly as hell, but these notes aren't going to be available
universally _ever_, so it's not like the crummy heuristic code gets to
go away.
Have you seen the APX spec?
>
https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html
It makes this even more fun because it adds a new XSAVE state component,
but reuses the MPX offsets.
> This information will be used by the debuggers to understand the XSAVE
> layout of the machine where the core file is dumped, and to read XSAVE
> registers, especially during cross-platform debugging.
This is pretty close to just a raw dump of the XSAVE CPUID leaves.
Rather than come up with an XSAVE-specific ABI that depends on CPUID
*ANYWAY* (because it dumps the "flags" register aka. ECX), maybe we
should just bite the bullet and dump out (some of) the raw CPUID space.
next prev parent reply other threads:[~2024-03-14 15:37 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-14 11:23 [PATCH 0/1] Add XSAVE layout description to Core files for debuggers to support varying XSAVE layouts Vignesh Balasubramanian
2024-03-14 11:23 ` [PATCH 1/1] x86/elf: Add a new .note section containing Xfeatures information to x86 core files Vignesh Balasubramanian
2024-03-14 15:37 ` Dave Hansen [this message]
2024-03-14 16:08 ` Borislav Petkov
2024-03-14 16:19 ` Dave Hansen
2024-03-14 16:29 ` Borislav Petkov
2024-03-14 16:39 ` Dave Hansen
2024-03-26 9:59 ` Balasubrmanian, Vignesh
2024-03-15 23:51 ` Thomas Gleixner
2024-03-16 10:29 ` Borislav Petkov
2024-03-14 16:45 ` John Baldwin
2024-03-14 17:10 ` Dave Hansen
2024-03-14 17:36 ` John Baldwin
2024-03-14 17:05 ` John Baldwin
2024-03-14 16:13 ` Kees Cook
2024-03-26 10:06 ` Balasubrmanian, Vignesh
2024-03-14 22:13 ` Michael Ellerman
2024-03-26 10:09 ` Balasubrmanian, Vignesh
2024-03-15 9:59 ` kernel test robot
2024-03-15 12:59 ` kernel test robot
2024-03-14 16:25 ` [PATCH 0/1] Add XSAVE layout description to Core files for debuggers to support varying XSAVE layouts Willgerodt, Felix
2024-03-14 16:33 ` Borislav Petkov
2024-03-15 8:43 ` Willgerodt, Felix
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