[linux-next:master 5634/13468] drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c:1782:2: warning: Value stored to 'dsc_common_mode' is never read [clang-analyzer-deadcode.DeadStores]

[linux-next:master 5634/13468] drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c:1782:2: warning: Value stored to 'dsc_common_mode' is never read [clang-analyzer-deadcode.DeadStores]

[kernel test robot]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head:   18ecd30af1a8402c162cca1bd58771c0e5be7815
commit: 58dca9810749480737869d02bef4704756372194 [5634/13468] drm/msm/disp/dpu1: Add support for DSC in encoder
config: arm-randconfig-c002-20220519 (https://download.01.org/0day-ci/archive/20220521/202205212108.0wSa0zTW-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project e00cbbec06c08dc616a0d52a20f678b8fbd4e304)
reproduce (this is a W=1 build):
         wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
         chmod +x ~/bin/make.cross
         # install arm cross compiling tool for clang build
         # apt-get install binutils-arm-linux-gnueabi
         # https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=58dca9810749480737869d02bef4704756372194
         git remote add linux-next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
         git fetch --no-tags linux-next master
         git checkout 58dca9810749480737869d02bef4704756372194
         # save the config file
         COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm clang-analyzer

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <yujie.liu@intel.com>


clang-analyzer warnings: (new ones prefixed by >>)

 >> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c:1782:2: warning: Value stored to 'dsc_common_mode' is never read [clang-analyzer-deadcode.DeadStores]
            dsc_common_mode = 0;
            ^                 ~

vim +/dsc_common_mode +1782 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

58dca981074948 Vinod Koul 2022-04-06  1757
58dca981074948 Vinod Koul 2022-04-06  1758  static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
58dca981074948 Vinod Koul 2022-04-06  1759  				 struct msm_display_dsc_config *dsc)
58dca981074948 Vinod Koul 2022-04-06  1760  {
58dca981074948 Vinod Koul 2022-04-06  1761  	/* coding only for 2LM, 2enc, 1 dsc config */
58dca981074948 Vinod Koul 2022-04-06  1762  	struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
58dca981074948 Vinod Koul 2022-04-06  1763  	struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
58dca981074948 Vinod Koul 2022-04-06  1764  	struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
58dca981074948 Vinod Koul 2022-04-06  1765  	int this_frame_slices;
58dca981074948 Vinod Koul 2022-04-06  1766  	int intf_ip_w, enc_ip_w;
58dca981074948 Vinod Koul 2022-04-06  1767  	int dsc_common_mode;
58dca981074948 Vinod Koul 2022-04-06  1768  	int pic_width;
58dca981074948 Vinod Koul 2022-04-06  1769  	u32 initial_lines;
58dca981074948 Vinod Koul 2022-04-06  1770  	int i;
58dca981074948 Vinod Koul 2022-04-06  1771
58dca981074948 Vinod Koul 2022-04-06  1772  	for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
58dca981074948 Vinod Koul 2022-04-06  1773  		hw_pp[i] = dpu_enc->hw_pp[i];
58dca981074948 Vinod Koul 2022-04-06  1774  		hw_dsc[i] = dpu_enc->hw_dsc[i];
58dca981074948 Vinod Koul 2022-04-06  1775
58dca981074948 Vinod Koul 2022-04-06  1776  		if (!hw_pp[i] || !hw_dsc[i]) {
58dca981074948 Vinod Koul 2022-04-06  1777  			DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n");
58dca981074948 Vinod Koul 2022-04-06  1778  			return;
58dca981074948 Vinod Koul 2022-04-06  1779  		}
58dca981074948 Vinod Koul 2022-04-06  1780  	}
58dca981074948 Vinod Koul 2022-04-06  1781
58dca981074948 Vinod Koul 2022-04-06 @1782  	dsc_common_mode = 0;
58dca981074948 Vinod Koul 2022-04-06  1783  	pic_width = dsc->drm->pic_width;
58dca981074948 Vinod Koul 2022-04-06  1784
58dca981074948 Vinod Koul 2022-04-06 @1785  	dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL;
58dca981074948 Vinod Koul 2022-04-06  1786  	if (enc_master->intf_mode == INTF_MODE_VIDEO)
58dca981074948 Vinod Koul 2022-04-06  1787  		dsc_common_mode |= DSC_MODE_VIDEO;
58dca981074948 Vinod Koul 2022-04-06  1788
58dca981074948 Vinod Koul 2022-04-06  1789  	this_frame_slices = pic_width / dsc->drm->slice_width;
58dca981074948 Vinod Koul 2022-04-06  1790  	intf_ip_w = this_frame_slices * dsc->drm->slice_width;
58dca981074948 Vinod Koul 2022-04-06  1791
58dca981074948 Vinod Koul 2022-04-06  1792  	/*
58dca981074948 Vinod Koul 2022-04-06  1793  	 * dsc merge case: when using 2 encoders for the same stream,
58dca981074948 Vinod Koul 2022-04-06  1794  	 * no. of slices need to be same on both the encoders.
58dca981074948 Vinod Koul 2022-04-06  1795  	 */
58dca981074948 Vinod Koul 2022-04-06  1796  	enc_ip_w = intf_ip_w / 2;
58dca981074948 Vinod Koul 2022-04-06  1797  	initial_lines = dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
58dca981074948 Vinod Koul 2022-04-06  1798
58dca981074948 Vinod Koul 2022-04-06  1799  	for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
58dca981074948 Vinod Koul 2022-04-06  1800  		dpu_encoder_dsc_pipe_cfg(hw_dsc[i], hw_pp[i], dsc, dsc_common_mode, initial_lines);
58dca981074948 Vinod Koul 2022-04-06  1801  }
58dca981074948 Vinod Koul 2022-04-06  1802

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