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h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=ANXZTmBqTf8HI/HKF9dMFDX1JKYT9msnV3dPOC3PjhI9N/PKNa22meDy3wy5D0Zwk 59tlyPbMOUQWsR6OEexT2W7g34t01O7uEJU1hFniwiWkQLrNduY0UXBRvXoaHz2kfw ETs4QiZD2enhPoPkrdk/djJ9pPUhqcMcAwdtIYrX+GkvJdY2E6ZkAen9iN19RBiz18 0hUXfiVOM43fFp0exxlS/brELMrf+O4b0APPpVTB1DNZx6HyfEi5t2A6y3e4FAfbgU g7XSF8TFM2tjrm0Qq4fqkCiZvv5wIncRxnvpZfEOD3Sc4suVXc67xtQcP4ObCtgp0X wGHCQoEoE9JJA== Message-ID: From: sashiko-bot@kernel.org Subject: Re: [PATCH RFC v10 10/22] arm64: Enable kpkeys Reply-To: sashiko-reviews@lists.linux.dev To: "Kevin Brodsky" Cc: "Andrew Morton" , "Ard Biesheuvel" , "Andy Lutomirski" , "Catalin Marinas" , "Dave Hansen" , =?utf-8?b?RGF2aWQgSGlsZGVuYnJh?= =?utf-8?b?bmQgKEFybSk=?= , "Jann Horn" , "Jeff Xu" , "Joey Gouly" , "Kees Cook" , "Linu Cherian" , "Linus Walleij" , "Marc Zyngier" , "Mark Brown" , "Matthew Wilcox" , "Maxwell Bland" , =?utf-8?b?TWlrZSBSYXBvcG9ydCAoSUJNKQ==?= , "Peter Zijlstra" , "Pierre Langlois" , =?utf-8?b?UGllcnJlLUNsw6ltZW50IFRv?= =?utf-8?b?c2k=?= , "Quentin Perret" , "Rick Edgecombe" , "Ryan Roberts" , "Vlastimil Babka" , "Will Deacon" , "Yang Shi" , "Yeoreum Yun" , linux-mm@kvack.org, x86@kernel.org, "Ira Weiny" , "Lorenzo Stoakes" , "Thomas Gleixner" In-Reply-To: <20261109-kpkeys-v10-10-aa6c4d9603bc@arm.com> References: <20261109-kpkeys-v10-0-aa6c4d9603bc@arm.com> <20261109-kpkeys-v10-10-aa6c4d9603bc@arm.com> Content-Type: text/plain; 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Sashiko AI review found 1 potential issue to consider: - [Medium] arm64: cpufeature: cpu_enable_poe() enables TCR2_EL1_POE without S1PIE -- commit 916b4efd6b8494c5d63fd0effff9032def1dba2d Author: Kevin Brodsky arm64: Enable kpkeys This commit enables POE at EL1 by initializing POR_EL1, setting TCR2_EL1.POE in cpu_enable_poe(), and selecting ARCH_HAS_KPKEYS under CONFIG_ARM64_POE. > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeatur= e.c > index 34c5c03c0c9b4..42d693197739c 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c [ ... ] > @@ -2334,8 +2335,10 @@ static void cpu_enable_mops(const struct arm64_cpu= _capabilities *__unused) > #ifdef CONFIG_ARM64_POE > static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) > { > - sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1_E0POE); > + write_sysreg_s(POR_EL1_INIT, SYS_POR_EL1); > + sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1_E0POE | TCR2_EL1_POE); > sysreg_clear_set(CPACR_EL1, 0, CPACR_EL1_E0POE); > + isb(); > } > #endif [Severity: Medium] Does enabling TCR2_EL1_POE here break privileged EL1 accesses to user memory when S1POE is present without S1PIE (for example, in a KVM guest configured with FEAT_S1POE=3D1 and FEAT_S1PIE=3D0)? Commit "arm64: mm: Enable overlays for all EL1 indirect permissions" relies on PIR_EL1 (PIE_E1) leaving user memory types without overlay (_O) so that privileged EL1 accesses to user pages (such as futex_atomic_op_inuser() using uaccess_enable_privileged() when FEAT_LSUI is absent) are not checked against POR_EL1. When S1PIE is absent, stage-1 translations use direct permissions and TCR2_EL1_POE applies POR_EL1 to all privileged accesses, including TTBR0 user mappings. Because POR_EL1_INIT only permits pkey 0, a user mapping with pkey 1..7 causes futex_atomic_op_inuser() to fault against POR_EL1 while fault_in_user_writeable() succeeds with unprivileged sttr against POR_EL0, resulting in an unbounded retry loop in futex_wake_op(). Should TCR2_EL1_POE and arch_supports_kpkeys() (or ARM64_HAS_S1POE itself) require S1PIE to be supported and enabled? --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20261109-kpkeys-v10= -0-aa6c4d9603bc@arm.com?part=3D10