Re: 2.4: why is NR_GFPINDEX so large?

Timur Tabi
2000-06-21T21:43:57Z

** Reply to message from Kanoj Sarcar <kanoj@google.engr.sgi.com> on Wed, 21
Jun 2000 14:41:16 -0700 (PDT)

> Which is hard to do with all the various architectures with varying
> cache line sizes out there. The asm header files can conveniently use
> __attribute__((aligned(128))) etc, but I think the generic header files
> use something like __attribute__((__aligned__(SMP_CACHE_BYTES))).
> Note that SMP_CACHE_BYTES is equated to the >> L1 << cache size for
> most architectures, which probably has a different effect than
> aligning on L2 cache lines.

Is the majority of the kernel cache-line aligned like this, or is this an area
where the kernel needs a lot of work?

--
Timur Tabi - ttabi@interactivesi.com
Interactive Silicon - http://www.interactivesi.com

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