From mboxrd@z Thu Jan  1 00:00:00 1970
From: Dinh Nguyen <dinguyen@altera.com>
Subject: Re: [PATCHv3 1/3] mmc: dw_mmc: Enable the hold reg for certain
 speed modes
Date: Mon, 9 Dec 2013 10:15:31 -0600
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To: Heiko =?ISO-8859-1?Q?St=FCbner?= <heiko@sntech.de>
Cc: dinh.linux@gmail.com, arnd@arndb.de, cjb@laptop.org, jh80.chung@samsung.com, tgih.jun@samsung.com, dianders@chromium.org, alim.akhtar@samsung.com, bzhao@marvell.com, linux-mmc@vger.kernel.org

On Mon, 2013-12-09 at 10:56 +0100, Heiko St=C3=BCbner wrote:
> Hi,
>=20
> Am Montag, 9. Dezember 2013, 05:51:06 schrieb dinguyen@altera.com:
> > From: Dinh Nguyen <dinguyen@altera.com>
> >=20
> > This patch will enable the SDMMC_CMD_USE_HOLD_REG bit when the slot=
 is
> > operating all timing modes, except for SDR50, DDR50, SDR104, and MM=
C_HS200.
> >=20
> > According to the Synopsys databook :"To meet the relatively high In=
put Hold
> > Time requirement for SDR12, SDR25, and other MMC speed modes, you s=
hould
> > program bit[29]use_hold_Reg of the CMD register to 1'b1;"..."Howeve=
r, for
> > the higher speed modes of SDR104, SDR50 and DDR50, you can meet the=
 much
> > smaller Input Hold Time requirement of 0.8ns by bypassing the Hold =
Register
> > (Path A in Figure 10-8, programming CMD.use_hold_reg =3D 1'b0) and =
then
> > adding delay elements on the output path as indicated.
> >=20
> > Also, "Never set CMD.use_hold_reg =3D 1 and cclk_in_drv phase shift=
 to 0 at
> > the same time. This would add an extra one-cycle delay on the outpu=
t path,
> > resulting in incorrect behavior."
> >=20
> > This patch also checks the IHR(Implement Hold Register) in the HCON
> > register.
> >=20
> > This information is taking from the v2.50a of the Synopsys Designwa=
re Cores
> > Mobile Storage Host Databook.
> >=20
> > Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> > Acked-by: Heiko Stuebner <heiko@sntech.de>
> > Tested-by: Heiko Stuebner <heiko@sntech.de>
> > ---
> > v3: Read the IHR(Implement Hold Register) in the HCON
> > v2: Add check for cclk_in_drv phase shift in conjunction with use_h=
old_reg.
>=20
> just to say it still works with the v3 changes.

Thanks for testing.
>=20
> Interestingly, the rockchip manual does not specify the hcon register=
 at all,=20
> but reading it, I get a value of 0x4c534c1 - letting BIT(22) be the r=
equired=20
> one.

I believe that the hcon register is there for all versions of this IP,
as the driver is reading this register to get the bus data width.

But then again there this comment before the read:
/*
 * Get the host data width - this assumes that HCON has been set with
 * the correct values.
*/

Dinh
>=20
>=20
> Heiko
>=20