* [PATCH] sdhci-of-esdhc: Support 8BIT bus width.
@ 2015-04-20 21:11 Joakim Tjernlund
2015-05-05 8:34 ` Ulf Hansson
0 siblings, 1 reply; 6+ messages in thread
From: Joakim Tjernlund @ 2015-04-20 21:11 UTC (permalink / raw)
To: linux-mmc; +Cc: Joakim Tjernlund
Signed-off-by: Joakim Tjernlund <joakim.tjernlund@transmode.se>
---
drivers/mmc/host/sdhci-of-esdhc.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
index 22e9111..7130130 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -82,6 +82,10 @@ static u8 esdhc_readb(struct sdhci_host *host, int reg)
/* fixup the result */
ret &= ~SDHCI_CTRL_DMA_MASK;
ret |= dma_bits;
+
+ /* 8BIT is bit 29 in Control register */
+ ret |= ((ret << 3) & SDHCI_CTRL_8BITBUS);
+ ret &= ~(SDHCI_CTRL_8BITBUS >> 3);
}
return ret;
@@ -134,6 +138,10 @@ static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)
dma_bits);
val &= ~SDHCI_CTRL_DMA_MASK;
val |= in_be32(host->ioaddr + reg) & SDHCI_CTRL_DMA_MASK;
+
+ /* 8BIT is bit 29 in Control register */
+ val |= ((val & SDHCI_CTRL_8BITBUS) >> 3);
+ val = (val & ~SDHCI_CTRL_8BITBUS);
}
/* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */
@@ -252,6 +260,8 @@ static void esdhc_of_platform_init(struct sdhci_host *host)
if (vvn > VENDOR_V_22)
host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
+
+ host->mmc->caps |= MMC_CAP_8_BIT_DATA;
}
static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
--
2.0.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] sdhci-of-esdhc: Support 8BIT bus width.
2015-04-20 21:11 [PATCH] sdhci-of-esdhc: Support 8BIT bus width Joakim Tjernlund
@ 2015-05-05 8:34 ` Ulf Hansson
2015-05-05 9:04 ` Joakim Tjernlund
0 siblings, 1 reply; 6+ messages in thread
From: Ulf Hansson @ 2015-05-05 8:34 UTC (permalink / raw)
To: Joakim Tjernlund; +Cc: linux-mmc
On 20 April 2015 at 23:11, Joakim Tjernlund
<joakim.tjernlund@transmode.se> wrote:
> Signed-off-by: Joakim Tjernlund <joakim.tjernlund@transmode.se>
Thanks, applied.
Kind regards
Uffe
> ---
> drivers/mmc/host/sdhci-of-esdhc.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
> index 22e9111..7130130 100644
> --- a/drivers/mmc/host/sdhci-of-esdhc.c
> +++ b/drivers/mmc/host/sdhci-of-esdhc.c
> @@ -82,6 +82,10 @@ static u8 esdhc_readb(struct sdhci_host *host, int reg)
> /* fixup the result */
> ret &= ~SDHCI_CTRL_DMA_MASK;
> ret |= dma_bits;
> +
> + /* 8BIT is bit 29 in Control register */
> + ret |= ((ret << 3) & SDHCI_CTRL_8BITBUS);
> + ret &= ~(SDHCI_CTRL_8BITBUS >> 3);
> }
>
> return ret;
> @@ -134,6 +138,10 @@ static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)
> dma_bits);
> val &= ~SDHCI_CTRL_DMA_MASK;
> val |= in_be32(host->ioaddr + reg) & SDHCI_CTRL_DMA_MASK;
> +
> + /* 8BIT is bit 29 in Control register */
> + val |= ((val & SDHCI_CTRL_8BITBUS) >> 3);
> + val = (val & ~SDHCI_CTRL_8BITBUS);
> }
>
> /* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */
> @@ -252,6 +260,8 @@ static void esdhc_of_platform_init(struct sdhci_host *host)
>
> if (vvn > VENDOR_V_22)
> host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
> +
> + host->mmc->caps |= MMC_CAP_8_BIT_DATA;
> }
>
> static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
> --
> 2.0.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] sdhci-of-esdhc: Support 8BIT bus width.
2015-05-05 8:34 ` Ulf Hansson
@ 2015-05-05 9:04 ` Joakim Tjernlund
2015-05-05 10:11 ` Ulf Hansson
0 siblings, 1 reply; 6+ messages in thread
From: Joakim Tjernlund @ 2015-05-05 9:04 UTC (permalink / raw)
To: ulf.hansson@linaro.org; +Cc: linux-mmc@vger.kernel.org
On Tue, 2015-05-05 at 10:34 +0200, Ulf Hansson wrote:
> On 20 April 2015 at 23:11, Joakim Tjernlund
> <joakim.tjernlund@transmode.se> wrote:
> > Signed-off-by: Joakim Tjernlund <joakim.tjernlund@transmode.se>
>
> Thanks, applied.
>
> Kind regards
> Uffe
Argh, I just learned that this patch is buggy. Please "unapply"
Jocke
>
>
> > ---
> > drivers/mmc/host/sdhci-of-esdhc.c | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
> > index 22e9111..7130130 100644
> > --- a/drivers/mmc/host/sdhci-of-esdhc.c
> > +++ b/drivers/mmc/host/sdhci-of-esdhc.c
> > @@ -82,6 +82,10 @@ static u8 esdhc_readb(struct sdhci_host *host, int reg)
> > /* fixup the result */
> > ret &= ~SDHCI_CTRL_DMA_MASK;
> > ret |= dma_bits;
> > +
> > + /* 8BIT is bit 29 in Control register */
> > + ret |= ((ret << 3) & SDHCI_CTRL_8BITBUS);
> > + ret &= ~(SDHCI_CTRL_8BITBUS >> 3);
> > }
> >
> > return ret;
> > @@ -134,6 +138,10 @@ static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)
> > dma_bits);
> > val &= ~SDHCI_CTRL_DMA_MASK;
> > val |= in_be32(host->ioaddr + reg) & SDHCI_CTRL_DMA_MASK;
> > +
> > + /* 8BIT is bit 29 in Control register */
> > + val |= ((val & SDHCI_CTRL_8BITBUS) >> 3);
> > + val = (val & ~SDHCI_CTRL_8BITBUS);
> > }
> >
> > /* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */
> > @@ -252,6 +260,8 @@ static void esdhc_of_platform_init(struct sdhci_host *host)
> >
> > if (vvn > VENDOR_V_22)
> > host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
> > +
> > + host->mmc->caps |= MMC_CAP_8_BIT_DATA;
> > }
> >
> > static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] sdhci-of-esdhc: Support 8BIT bus width.
2015-05-05 9:04 ` Joakim Tjernlund
@ 2015-05-05 10:11 ` Ulf Hansson
2015-05-05 12:22 ` Joakim Tjernlund
0 siblings, 1 reply; 6+ messages in thread
From: Ulf Hansson @ 2015-05-05 10:11 UTC (permalink / raw)
To: Joakim Tjernlund; +Cc: linux-mmc@vger.kernel.org
On 5 May 2015 at 11:04, Joakim Tjernlund <joakim.tjernlund@transmode.se> wrote:
> On Tue, 2015-05-05 at 10:34 +0200, Ulf Hansson wrote:
>> On 20 April 2015 at 23:11, Joakim Tjernlund
>> <joakim.tjernlund@transmode.se> wrote:
>> > Signed-off-by: Joakim Tjernlund <joakim.tjernlund@transmode.se>
>>
>> Thanks, applied.
>>
>> Kind regards
>> Uffe
>
> Argh, I just learned that this patch is buggy. Please "unapply"
>
> Jocke
>
Done!
Kind regards
Uffe
>>
>>
>> > ---
>> > drivers/mmc/host/sdhci-of-esdhc.c | 10 ++++++++++
>> > 1 file changed, 10 insertions(+)
>> >
>> > diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
>> > index 22e9111..7130130 100644
>> > --- a/drivers/mmc/host/sdhci-of-esdhc.c
>> > +++ b/drivers/mmc/host/sdhci-of-esdhc.c
>> > @@ -82,6 +82,10 @@ static u8 esdhc_readb(struct sdhci_host *host, int reg)
>> > /* fixup the result */
>> > ret &= ~SDHCI_CTRL_DMA_MASK;
>> > ret |= dma_bits;
>> > +
>> > + /* 8BIT is bit 29 in Control register */
>> > + ret |= ((ret << 3) & SDHCI_CTRL_8BITBUS);
>> > + ret &= ~(SDHCI_CTRL_8BITBUS >> 3);
>> > }
>> >
>> > return ret;
>> > @@ -134,6 +138,10 @@ static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)
>> > dma_bits);
>> > val &= ~SDHCI_CTRL_DMA_MASK;
>> > val |= in_be32(host->ioaddr + reg) & SDHCI_CTRL_DMA_MASK;
>> > +
>> > + /* 8BIT is bit 29 in Control register */
>> > + val |= ((val & SDHCI_CTRL_8BITBUS) >> 3);
>> > + val = (val & ~SDHCI_CTRL_8BITBUS);
>> > }
>> >
>> > /* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */
>> > @@ -252,6 +260,8 @@ static void esdhc_of_platform_init(struct sdhci_host *host)
>> >
>> > if (vvn > VENDOR_V_22)
>> > host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
>> > +
>> > + host->mmc->caps |= MMC_CAP_8_BIT_DATA;
>> > }
>> >
>> > static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] sdhci-of-esdhc: Support 8BIT bus width.
2015-05-05 10:11 ` Ulf Hansson
@ 2015-05-05 12:22 ` Joakim Tjernlund
2015-05-05 13:01 ` Ulf Hansson
0 siblings, 1 reply; 6+ messages in thread
From: Joakim Tjernlund @ 2015-05-05 12:22 UTC (permalink / raw)
To: ulf.hansson@linaro.org; +Cc: linux-mmc@vger.kernel.org
On Tue, 2015-05-05 at 12:11 +0200, Ulf Hansson wrote:
> On 5 May 2015 at 11:04, Joakim Tjernlund <joakim.tjernlund@transmode.se> wrote:
> > On Tue, 2015-05-05 at 10:34 +0200, Ulf Hansson wrote:
> > > On 20 April 2015 at 23:11, Joakim Tjernlund
> > > <joakim.tjernlund@transmode.se> wrote:
> > > > Signed-off-by: Joakim Tjernlund <joakim.tjernlund@transmode.se>
> > >
> > > Thanks, applied.
> > >
> > > Kind regards
> > > Uffe
> >
> > Argh, I just learned that this patch is buggy. Please "unapply"
> >
> > Jocke
> >
>
> Done!
Thanks, new version sent :)
BTW, can I ask, cat /sys/kernel/debug/mmc0/ios:
clock: 52000000 Hz
actual clock: 50000000 Hz
vdd: 7 (1.65 - 1.95 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 3 (8 bits)
timing spec: 1 (mmc high-speed)
signal voltage: 0 (3.30 V)
What is signal voltage: 0 (3.30 V) here ?
Jocke
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] sdhci-of-esdhc: Support 8BIT bus width.
2015-05-05 12:22 ` Joakim Tjernlund
@ 2015-05-05 13:01 ` Ulf Hansson
0 siblings, 0 replies; 6+ messages in thread
From: Ulf Hansson @ 2015-05-05 13:01 UTC (permalink / raw)
To: Joakim Tjernlund; +Cc: linux-mmc@vger.kernel.org
On 5 May 2015 at 14:22, Joakim Tjernlund <joakim.tjernlund@transmode.se> wrote:
> On Tue, 2015-05-05 at 12:11 +0200, Ulf Hansson wrote:
>> On 5 May 2015 at 11:04, Joakim Tjernlund <joakim.tjernlund@transmode.se> wrote:
>> > On Tue, 2015-05-05 at 10:34 +0200, Ulf Hansson wrote:
>> > > On 20 April 2015 at 23:11, Joakim Tjernlund
>> > > <joakim.tjernlund@transmode.se> wrote:
>> > > > Signed-off-by: Joakim Tjernlund <joakim.tjernlund@transmode.se>
>> > >
>> > > Thanks, applied.
>> > >
>> > > Kind regards
>> > > Uffe
>> >
>> > Argh, I just learned that this patch is buggy. Please "unapply"
>> >
>> > Jocke
>> >
>>
>> Done!
>
> Thanks, new version sent :)
>
> BTW, can I ask, cat /sys/kernel/debug/mmc0/ios:
> clock: 52000000 Hz
> actual clock: 50000000 Hz
> vdd: 7 (1.65 - 1.95 V)
> bus mode: 2 (push-pull)
> chip select: 0 (don't care)
> power mode: 2 (on)
> bus width: 3 (8 bits)
> timing spec: 1 (mmc high-speed)
> signal voltage: 0 (3.30 V)
>
> What is signal voltage: 0 (3.30 V) here ?
Since you are running in mmc high-speed mode, the 3.3V is the signal
voltage that is being used.
Kind regards
Uffe
^ permalink raw reply [flat|nested] 6+ messages in thread
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2015-04-20 21:11 [PATCH] sdhci-of-esdhc: Support 8BIT bus width Joakim Tjernlund
2015-05-05 8:34 ` Ulf Hansson
2015-05-05 9:04 ` Joakim Tjernlund
2015-05-05 10:11 ` Ulf Hansson
2015-05-05 12:22 ` Joakim Tjernlund
2015-05-05 13:01 ` Ulf Hansson
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