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From: Suman Tripathi <stripathi@apm.com>
To: chris@printf.net, anton@enomsg.org, arnd@arndb.de,
	michal.simek@xilinx.com
Cc: linux-mmc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	ddutile@redhat.com, jcm@redhat.com, mlangsdo@redhat.com,
	patches@apm.com, Suman Tripathi <stripathi@apm.com>
Subject: [PATCH v6 2/2] mmc: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0.
Date: Wed,  6 May 2015 19:12:11 +0530	[thread overview]
Message-ID: <1430919731-9016-3-git-send-email-stripathi@apm.com> (raw)
In-Reply-To: <1430919731-9016-1-git-send-email-stripathi@apm.com>

The sdhci framework disables SDR104/SDR50/DDR50 based on only quirk.
This patch adds the support to disable SDR104/SDR50/DDR50 based on
reading the capability register 0.

Signed-off-by: Suman Tripathi <stripathi@apm.com>
---
 drivers/mmc/host/sdhci.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index c80287a..e024c64 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -3199,7 +3199,8 @@ int sdhci_add_host(struct sdhci_host *host)
 		}
 	}

-	if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
+	if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V ||
+	    !(caps[0] & SDHCI_CAN_VDD_180))
 		caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 		       SDHCI_SUPPORT_DDR50);

--
1.8.2.1


  parent reply	other threads:[~2015-05-06 13:43 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-06 13:42 [PATCH v6 0/2] Add SDHCI support for APM X-Gene SoC using ARASAN SDHCI controller Suman Tripathi
     [not found] ` <1430919731-9016-1-git-send-email-stripathi-qTEPVZfXA3Y@public.gmane.org>
2015-05-06 13:42   ` [PATCH v6 1/2] arm64: dts: Add the arasan sdhci nodes in apm-storm.dtsi Suman Tripathi
2015-05-08  8:09     ` Suman Tripathi
2015-05-06 13:42 ` Suman Tripathi [this message]
2015-05-08  8:10   ` [PATCH v6 2/2] mmc: sdhci: Add support to disable SDR104/SDR50/DDR50 based on capability register 0 Suman Tripathi

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