From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexey Brodkin Subject: Re: [PATCH v2] mmc: dw_mmc: Fix the DTO timeout overflow calculation for 32-bit systems Date: Thu, 22 Feb 2018 16:03:35 +0000 Message-ID: <1519315414.19466.9.camel@synopsys.com> References: <20180222133418.29336-1-Evgeniy.Didin@synopsys.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Content-Language: en-US Content-ID: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+gla-linux-snps-arc=m.gmane.org@lists.infradead.org To: "Evgeniy.Didin@synopsys.com" Cc: "ulf.hansson@linaro.org" , "Vineet.Gupta1@synopsys.com" , "Alexey.Brodkin@synopsys.com" , "linux-mmc@vger.kernel.org" , "dianders@chromium.org" , "stable@vger.kernel.org" , "jh80.chung@samsung.com" , "linux-snps-arc@lists.infradead.org" , "Eugeniy.Paltsev@synopsys.com" , "shawn.lin@rock-chips.com" List-Id: linux-mmc@vger.kernel.org Hi Shawn, On Thu, 2018-02-22 at 23:28 +0800, Shawn Lin wrote: [snip] > > > Stack Trace: > > > arc_unwind_core.constprop.1+0xd0/0xf4 > > > dump_stack+0x68/0x80 > > > warn_slowpath_null+0x4e/0xec > > > sg_miter_next+0x28/0x20c > > > dw_mci_read_data_pio+0x44/0x190 > > > dw_mmc f000a000.mmc: Unexpected interrupt latency > > I think we tested SD cards but the main reason we missed > this is that we don't use pio mode since dw_mmc decides > the transfer mode via HCON register but we don't have one > platform at hand then to do that. Given the data-transfer-over > interrupt should come after the data hit the RAM, so pio mode > could probably consume more time than IDMAC. That's really interesting. I was under impression that we use internal DMA controller (AKA IDMAC) on that platform (HSDK). This is what we typically see in bootlog (this extract is taken from 4.15-r9): --------------------------------->8-------------------------------- dw_mmc f000a000.mmc: 'num-slots' was deprecated. dw_mmc f000a000.mmc: IDMAC supports 32-bit address mode. dw_mmc f000a000.mmc: Using internal DMA controller. dw_mmc f000a000.mmc: Version ID is 290a dw_mmc f000a000.mmc: DW MMC controller at irq 12,32 bit host data width,16 deep fifo --------------------------------->8-------------------------------- I'm not really sure how PIO mode (which stands for non-DMA mode) got used given we have IDMAC in the hardware. @ Evgeniy, could you please check why IDMAC is not used? -Alexey