Re: [PATCH] mmc: sdhci-pci-gli: fix GL9750 DMA write corruption

[Adrian Hunter <adrian.hunter@intel.com>]

On 27/02/2026 09:59, Matthew Schwartz wrote:
> The GL9750 SD host controller has intermittent data corruption during
> DMA write operations. The GM_BURST register's R_OSRC_Lmt field
> (bits 17:16), which limits outstanding DMA read requests from system
> memory, is not being cleared during initialization. The Windows driver
> sets R_OSRC_Lmt to zero, limiting requests to the smallest unit.
> 
> Clear R_OSRC_Lmt to match the Windows driver behavior. This eliminates
> write corruption verified with f3write/f3read tests while maintaining
> DMA performance.
> 
> Cc: stable@vger.kernel.org
> Fixes: e51df6ce668a ("mmc: host: sdhci-pci: Add Genesys Logic GL975x support")
> Closes: https://lore.kernel.org/linux-mmc/33d12807-5c72-41ce-8679-57aa11831fad@linux.dev/
> Signed-off-by: Matthew Schwartz <matthew.schwartz@linux.dev>

Ben wrote "So I think your patch setting R_OSRC_Lmt to zero is reasonable."
Can be have a Reviewed-by tag also?

Nevertheless:

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
> Link to RFC: https://lore.kernel.org/all/20260117234800.931664-1-matthew.schwartz@linux.dev/
> Changes from RFC -> v1: use the proper name for the register field 
> ---
>  drivers/mmc/host/sdhci-pci-gli.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
> index b0f91cc9e40e4..7a7be3f7bee6b 100644
> --- a/drivers/mmc/host/sdhci-pci-gli.c
> +++ b/drivers/mmc/host/sdhci-pci-gli.c
> @@ -26,6 +26,9 @@
>  #define   GLI_9750_WT_EN_ON	    0x1
>  #define   GLI_9750_WT_EN_OFF	    0x0
>  
> +#define SDHCI_GLI_9750_GM_BURST_SIZE		  0x510
> +#define   SDHCI_GLI_9750_GM_BURST_SIZE_R_OSRC_LMT	    GENMASK(17, 16)
> +
>  #define SDHCI_GLI_9750_CFG2          0x848
>  #define   SDHCI_GLI_9750_CFG2_L1DLY    GENMASK(28, 24)
>  #define   GLI_9750_CFG2_L1DLY_VALUE    0x1F
> @@ -629,6 +632,11 @@ static void gl9750_hw_setting(struct sdhci_host *host)
>  
>  	gl9750_wt_on(host);
>  
> +	/* clear R_OSRC_Lmt to avoid DMA write corruption */
> +	value = sdhci_readl(host, SDHCI_GLI_9750_GM_BURST_SIZE);
> +	value &= ~SDHCI_GLI_9750_GM_BURST_SIZE_R_OSRC_LMT;
> +	sdhci_writel(host, value, SDHCI_GLI_9750_GM_BURST_SIZE);
> +
>  	value = sdhci_readl(host, SDHCI_GLI_9750_CFG2);
>  	value &= ~SDHCI_GLI_9750_CFG2_L1DLY;
>  	/* set ASPM L1 entry delay to 7.9us */