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[82.65.169.74]) by smtp.gmail.com with ESMTPSA id u18-20020a05600c19d200b003c6f8d30e40sm17246093wmq.31.2022.11.13.12.40.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 12:40:56 -0800 (PST) References: <20221110150035.2824580-1-adeep@lexina.in> User-agent: mu4e 1.8.10; emacs 28.2 From: Jerome Brunet To: Vyacheslav Bocharov , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 0/4] arm64: amlogic: mmc: meson-gx: Add core, tx, rx Date: Sun, 13 Nov 2022 21:06:44 +0100 In-reply-to: <20221110150035.2824580-1-adeep@lexina.in> Message-ID: <1jk03y37vs.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org On Thu 10 Nov 2022 at 18:00, Vyacheslav Bocharov wrote: > The mmc driver use the same phase values (core - 180, tx/rx - 0) for all > meson64 platforms. However, some platforms (and even some boards) require > different values Where does it stops ? Trying to solve the instabilities of this IP/driver by tweaking the phase has proven to be dead-end. Soon, you'll end up tweaking these settings depending on the on particular version of the device because it ships with a different eMMC manufacturer. Then comes multi sourcing, sdio modules, sdcards ... > (axg for example use 270 degree for core clock). Where ? Upstream linux does not u-boot does something of the sort for sm1 and I'm not entirely sure this appropriate either. IMO, this setting has more to do with the mode the mmc device is operating at - not the platform or board. We had some discussions with the HW designers at AML and they recommended to keep a phase shift of 180 between the Core and Tx. They also recommended to leave Rx alone (actually, starting from the v3, the Rx field has no effect. It is not even wired to actual HW) Funnily, that is not what the vendor driver does. It also does A LOT of extremely complex and 'debatable' things, which mostly mask how much the driver is unstable. With the upstream drivers, modes up to SDR50 and HS200 have been stable lately. SDR104 and DDR modes (DDR52 or HS400) remains problematic. Changing the settings further would require more discussion with AML. Blindly poking these value until you get something stablish for 1 particular use case is a recipe for disaster. > This patch > transfers the values from the code to the variables in the device-tree files. > If not set in dts, use old default values. I think going that way is opening a big can of worms. I don't think this should be applied > > Vyacheslav Bocharov (4): > arm64: amlogic: mmc: meson-gx: Add core, tx, rx eMMC/SD/SDIO phase > clock settings from devicetree data > arm64: amlogic: mmc: meson-gx: Add dts binding include for core, tx, > rx eMMC/SD/SDIO phase clock settings from devicetree data > arm64: amlogic: dts: meson: update meson-axg device-tree for new core, > tx, rx phase clock settings. > arm64: dts: docs: Update mmc meson-gx documentation for new config > option amlogic,mmc-phase > > .../bindings/mmc/amlogic,meson-gx.txt | 7 ++++ > arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 3 ++ > drivers/mmc/host/meson-gx-mmc.c | 18 +++++++--- > include/dt-bindings/mmc/meson-gx-mmc.h | 35 +++++++++++++++++++ > 4 files changed, 58 insertions(+), 5 deletions(-) > create mode 100644 include/dt-bindings/mmc/meson-gx-mmc.h