From mboxrd@z Thu Jan  1 00:00:00 1970
From: Andrew Morton <akpm@linux-foundation.org>
Subject: Re: [PATCH v3] MMC: Add JZ4740 mmc driver
Date: Wed, 30 Jun 2010 13:55:25 -0700
Message-ID: <20100630135525.1f6a9704.akpm@linux-foundation.org>
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To: Lars-Peter Clausen <lars@metafoo.de>
Cc: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Matt Fleming <matt@console-pimps.org>, linux-mmc@vger.kernel.org

On Mon, 28 Jun 2010 03:20:41 +0200
Lars-Peter Clausen <lars@metafoo.de> wrote:

> This patch adds support for the mmc controller on JZ4740 SoCs.
> 
> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
> Cc: Andrew Morton <akpm@linux-foundation.org>
> Cc: Matt Fleming <matt@console-pimps.org>
> Cc: linux-mmc@vger.kernel.org
>
> ...
>
> +#define JZ4740_MMC_MAX_TIMEOUT 10000000

That was a really big timeout.  How long do 1e7 readw's take?  Oh well.

>
> ...
>
> +static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
> +{
> +	uint32_t status;
> +
> +	writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
> +	do {
> +		status = readl(host->base + JZ_REG_MMC_STATUS);
> +	} while (status & JZ_MMC_STATUS_CLK_EN);
> +}
> +
> +static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
> +{
> +	uint32_t status;
> +
> +	writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
> +	udelay(10);
> +	do {
> +		status = readl(host->base + JZ_REG_MMC_STATUS);
> +	} while (status & JZ_MMC_STATUS_IS_RESETTING);
> +}

Maybe these should have a timeout too?

>
> ...
>
> +static inline unsigned int jz4740_mmc_wait_irq(struct jz4740_mmc_host *host,
> +	unsigned int irq)
> +{
> +	unsigned int timeout = JZ4740_MMC_MAX_TIMEOUT;
> +	uint16_t status;
> +
> +	do {
> +		status = readw(host->base + JZ_REG_MMC_IREG);
> +	} while (!(status & irq) && --timeout);
> +
> +	return timeout;
> +}

This guy's too big to inline.  Recent gcc's know that and they tend to
uninline such things behind your back anwyay.

>
> ...
>
> +struct jz4740_mmc_platform_data {
> +	int gpio_power;
> +	int gpio_card_detect;
> +	int gpio_read_only;
> +	unsigned card_detect_active_low:1;
> +	unsigned read_only_active_low:1;
> +	unsigned power_active_low:1;
> +
> +	unsigned data_1bit:1;
> +};

The bitfields will all share the same word, so modification of one
field can race against modification of another field.  Hence some form
of locking which covers *all* the bitfields is needed.

Is that a problem in this driver?