* [PATCH 0/2] Add GPIO WP and HW bus-width caps when support i.MX51 BBG board
@ 2010-10-20 10:00 Richard Zhu
2010-10-20 10:00 ` [PATCH 1/2] Add the GPIO Write Protection Solution on " Richard Zhu
[not found] ` <010C9052C42A00499CE76D637FA5EE90A516@039-SN1MPN1-002.039d.mgd.msft.net>
0 siblings, 2 replies; 5+ messages in thread
From: Richard Zhu @ 2010-10-20 10:00 UTC (permalink / raw)
To: linux-mmc, linux-arm-kernel, eric, w.sang; +Cc: r65037
This serial patches are based on Wolfram and Eric's eSDHC driver patchs, and
add the GPIO Write Protection, and HW bus-width cpas supports on i.MX51
BBG boards.
[PATCH 1/2] Add the GPIO Write Protection Solution on i.MX51 BBG board
arch/arm/mach-mx5/board-mx51_babbage.c | 16 ++++++++++++++--
arch/arm/plat-mxc/include/mach/iomux-mx51.h | 8 +++++---
2 files changed, 19 insertions(+), 5 deletions(-)
[PATCH 2/2] Add the HW board caps flag for MX51 BBG
arch/arm/mach-mx5/board-mx51_babbage.c | 3 +++
arch/arm/plat-mxc/include/mach/esdhc.h | 1 +
drivers/mmc/host/sdhci-esdhc-imx.c | 1 +
drivers/mmc/host/sdhci.c | 8 ++++++--
4 files changed, 11 insertions(+), 2 deletions(-)
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] Add the GPIO Write Protection Solution on i.MX51 BBG board
2010-10-20 10:00 [PATCH 0/2] Add GPIO WP and HW bus-width caps when support i.MX51 BBG board Richard Zhu
@ 2010-10-20 10:00 ` Richard Zhu
2010-10-20 10:00 ` [PATCH 2/2] Add the HW board caps flag for MX51 BBG Richard Zhu
2010-10-20 10:24 ` [PATCH 1/2] Add the GPIO Write Protection Solution on i.MX51 BBG board Baruch Siach
[not found] ` <010C9052C42A00499CE76D637FA5EE90A516@039-SN1MPN1-002.039d.mgd.msft.net>
1 sibling, 2 replies; 5+ messages in thread
From: Richard Zhu @ 2010-10-20 10:00 UTC (permalink / raw)
To: linux-mmc, linux-arm-kernel, eric, w.sang; +Cc: r65037
---
arch/arm/mach-mx5/board-mx51_babbage.c | 16 ++++++++++++++--
arch/arm/plat-mxc/include/mach/iomux-mx51.h | 8 +++++---
2 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index 476bfe4..5a69cda 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -34,6 +34,8 @@
#include "devices-imx51.h"
#include "devices.h"
+#define BABBAGE_SDHCI1_WP (0*32 + 1) /* GPIO_1_1 */
+#define BABBAGE_SDHCI2_WP (0*32 + 5) /* GPIO_1_5 */
#define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */
#define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */
#define BABBAGE_PHY_RESET (1*32 +5) /* GPIO_2_5 */
@@ -102,6 +104,7 @@ static struct pad_desc mx51babbage_pads[] = {
MX51_PAD_SD1_DATA1__SD1_DATA1,
MX51_PAD_SD1_DATA2__SD1_DATA2,
MX51_PAD_SD1_DATA3__SD1_DATA3,
+ MX51_PAD_GPIO_1_1__GPIO_1_1,
/* SD 2 */
MX51_PAD_SD2_CMD__SD2_CMD,
@@ -110,6 +113,7 @@ static struct pad_desc mx51babbage_pads[] = {
MX51_PAD_SD2_DATA1__SD2_DATA1,
MX51_PAD_SD2_DATA2__SD2_DATA2,
MX51_PAD_SD2_DATA3__SD2_DATA3,
+ MX51_PAD_GPIO_1_5__GPIO_1_5,
};
/* Serial ports */
@@ -257,6 +261,14 @@ static int __init babbage_otg_mode(char *options)
}
__setup("otg_mode=", babbage_otg_mode);
+static struct esdhc_platform_data esdhc_imx_pdata1 = {
+ .wp_gpio = BABBAGE_SDHCI1_WP,
+};
+
+static struct esdhc_platform_data esdhc_imx_pdata2 = {
+ .wp_gpio = BABBAGE_SDHCI2_WP,
+};
+
/*
* Board specific initialization.
*/
@@ -286,8 +298,8 @@ static void __init mxc_board_init(void)
mxc_iomux_v3_setup_pad(&usbh1stp);
babbage_usbhub_reset();
- imx51_add_esdhc(0, NULL);
- imx51_add_esdhc(1, NULL);
+ imx51_add_esdhc(0, &esdhc_imx_pdata1);
+ imx51_add_esdhc(1, &esdhc_imx_pdata2);
}
static void __init mx51_babbage_timer_init(void)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index 935f790..a3d84ad 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -43,7 +43,7 @@ typedef enum iomux_config {
#define MX51_USBH1_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_PKE | PAD_CTL_HYS)
-#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \
+#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \
PAD_CTL_SRE_FAST)
#define MX51_SDHCI_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \
PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_SRE_FAST | \
@@ -310,7 +310,8 @@ typedef enum iomux_config {
#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, IOMUX_CONFIG_SION, 0x0, 0, \
MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, IOMUX_CONFIG_GPIO, 0x0, 0, \
+ MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, IOMUX_CONFIG_SION, 0x0, 1, \
MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, IOMUX_CONFIG_SION, 0x0, 0, \
@@ -331,7 +332,8 @@ typedef enum iomux_config {
0x9bc, 3, MX51_I2C_PAD_CTRL)
#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, IOMUX_CONFIG_GPIO, 0x0, 1, \
+ MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, MX51_GPIO_PAD_CTRL)
--
1.6.3.3
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] Add the HW board caps flag for MX51 BBG
2010-10-20 10:00 ` [PATCH 1/2] Add the GPIO Write Protection Solution on " Richard Zhu
@ 2010-10-20 10:00 ` Richard Zhu
2010-10-20 10:24 ` [PATCH 1/2] Add the GPIO Write Protection Solution on i.MX51 BBG board Baruch Siach
1 sibling, 0 replies; 5+ messages in thread
From: Richard Zhu @ 2010-10-20 10:00 UTC (permalink / raw)
To: linux-mmc, linux-arm-kernel, eric, w.sang; +Cc: r65037
Some HW boards may have the bus-width caps limitation in HW design refer
to the caps of the IC module.
For example, the MAX BUS width the eSDHC module on i.MX51 is up to
8bits.
But only the 1/4bits bus are supported on i.MX51 BBG boards.
Signed-off-by: Richard Zhu <r65037@freescale.com>
---
arch/arm/mach-mx5/board-mx51_babbage.c | 3 +++
arch/arm/plat-mxc/include/mach/esdhc.h | 1 +
drivers/mmc/host/sdhci-esdhc-imx.c | 1 +
drivers/mmc/host/sdhci.c | 8 ++++++--
4 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index 5a69cda..9261ce9 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -24,6 +24,7 @@
#include <mach/iomux-mx51.h>
#include <mach/i2c.h>
#include <mach/mxc_ehci.h>
+#include <mach/mmc.h>
#include <asm/irq.h>
#include <asm/setup.h>
@@ -263,10 +264,12 @@ __setup("otg_mode=", babbage_otg_mode);
static struct esdhc_platform_data esdhc_imx_pdata1 = {
.wp_gpio = BABBAGE_SDHCI1_WP,
+ .caps = MMC_CAP_4_BIT_DATA,
};
static struct esdhc_platform_data esdhc_imx_pdata2 = {
.wp_gpio = BABBAGE_SDHCI2_WP,
+ .caps = MMC_CAP_4_BIT_DATA,
};
/*
diff --git a/arch/arm/plat-mxc/include/mach/esdhc.h b/arch/arm/plat-mxc/include/mach/esdhc.h
index a48a9aa..de6e84b 100644
--- a/arch/arm/plat-mxc/include/mach/esdhc.h
+++ b/arch/arm/plat-mxc/include/mach/esdhc.h
@@ -12,5 +12,6 @@
struct esdhc_platform_data {
unsigned int wp_gpio; /* write protect pin */
+ unsigned int caps; /* hw board esdhc caps */
};
#endif /* __ASM_ARCH_IMX_ESDHC_H */
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 6556762..1f80936 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -129,6 +129,7 @@ static int esdhc_pltfm_init(struct sdhci_host *host, struct sdhci_pltfm_data *pd
if (boarddata) {
gpio_request(boarddata->wp_gpio, "SD_WP");
gpio_direction_input(boarddata->wp_gpio);
+ host->caps |= boarddata->caps;
}
return 0;
}
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 782c0ee..7c12442 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1848,8 +1848,12 @@ int sdhci_add_host(struct sdhci_host *host)
mmc->f_max = host->max_clk;
mmc->caps |= MMC_CAP_SDIO_IRQ;
- if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
- mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
+ if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) {
+ if (host->caps & MMC_CAP_8_BIT_DATA)
+ mmc->caps |= MMC_CAP_8_BIT_DATA;
+ if (host->caps & MMC_CAP_4_BIT_DATA)
+ mmc->caps |= MMC_CAP_4_BIT_DATA;
+ }
if (caps & SDHCI_CAN_DO_HISPD)
mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
--
1.6.3.3
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] Add the GPIO Write Protection Solution on i.MX51 BBG board
2010-10-20 10:00 ` [PATCH 1/2] Add the GPIO Write Protection Solution on " Richard Zhu
2010-10-20 10:00 ` [PATCH 2/2] Add the HW board caps flag for MX51 BBG Richard Zhu
@ 2010-10-20 10:24 ` Baruch Siach
1 sibling, 0 replies; 5+ messages in thread
From: Baruch Siach @ 2010-10-20 10:24 UTC (permalink / raw)
To: Richard Zhu; +Cc: linux-mmc, linux-arm-kernel, eric, w.sang
Hi Richard,
On Wed, Oct 20, 2010 at 06:00:27PM +0800, Richard Zhu wrote:
> ---
> arch/arm/mach-mx5/board-mx51_babbage.c | 16 ++++++++++++++--
> arch/arm/plat-mxc/include/mach/iomux-mx51.h | 8 +++++---
> 2 files changed, 19 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
> index 476bfe4..5a69cda 100644
> --- a/arch/arm/mach-mx5/board-mx51_babbage.c
> +++ b/arch/arm/mach-mx5/board-mx51_babbage.c
> @@ -34,6 +34,8 @@
> #include "devices-imx51.h"
> #include "devices.h"
>
> +#define BABBAGE_SDHCI1_WP (0*32 + 1) /* GPIO_1_1 */
> +#define BABBAGE_SDHCI2_WP (0*32 + 5) /* GPIO_1_5 */
Please mention in the subject of this patch that this "write protection" is
related to the SDHCI device.
baruch
--
~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- baruch@tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 0/2] Add GPIO WP and HW bus-width caps when support i.MX51 BBG board
[not found] ` <010C9052C42A00499CE76D637FA5EE90A516@039-SN1MPN1-002.039d.mgd.msft.net>
@ 2010-11-03 14:06 ` Wolfram Sang
0 siblings, 0 replies; 5+ messages in thread
From: Wolfram Sang @ 2010-11-03 14:06 UTC (permalink / raw)
To: Zhu Richard-R65037; +Cc: linux-mmc
[-- Attachment #1: Type: text/plain, Size: 832 bytes --]
Hi Richard,
> Do you have any comments about the following patches?
> These patches add the GPIO write protection, and add the HW bus-width
> caps limitation.
First patch: The sdhci-part is okay (it's trivial enough), did not check
the iomux-stuff, but I assume it works for you :) If you are basing your
patch on my RFC-patches, it would be better for the process if you'd a)
note the dependency in your patch and b) add some Acked-by or Tested-by
to my original series.
Second patch: There is some discussion about the bus width currently
going on. I'd suggest you join it.
BTW did you try adding regulator support yet?
Best regards,
Wolfram
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 198 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
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2010-10-20 10:00 [PATCH 0/2] Add GPIO WP and HW bus-width caps when support i.MX51 BBG board Richard Zhu
2010-10-20 10:00 ` [PATCH 1/2] Add the GPIO Write Protection Solution on " Richard Zhu
2010-10-20 10:00 ` [PATCH 2/2] Add the HW board caps flag for MX51 BBG Richard Zhu
2010-10-20 10:24 ` [PATCH 1/2] Add the GPIO Write Protection Solution on i.MX51 BBG board Baruch Siach
[not found] ` <010C9052C42A00499CE76D637FA5EE90A516@039-SN1MPN1-002.039d.mgd.msft.net>
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