* [PATCH 2/3] mmc, sh: Correct value for reset
2010-11-26 23:02 [PATCH 1/3] sh, mmc: Make mmcif_update_progress static inline Simon Horman
@ 2010-11-26 23:02 ` Simon Horman
2010-11-26 23:02 ` [PATCH 3/3] sh, mmc: Use defines when setting CE_CLK_CTRL Simon Horman
2010-11-29 3:55 ` [PATCH 1/3] sh, mmc: Make mmcif_update_progress static inline Paul Mundt
2 siblings, 0 replies; 8+ messages in thread
From: Simon Horman @ 2010-11-26 23:02 UTC (permalink / raw)
To: linux-mmc, linux-sh
Cc: Yusuke Goda, Magnus Damm, Kuninori Morimoto, Chris Ball,
Paul Mundt, Simon Horman
This resolves a regression that I introduced in
"mmc, sh: Move constants to sh_mmcif.h". Having
examined the manual and tested the code on an AP4EVB board
it seems that the correct sequence is.
1) Write 1 to bit 31 and zeros to all other bits
2) Write zero to all bits
Cc: Yusuke Goda <yusuke.goda.sx@renesas.com>
Cc: Magnus Damm <magnus.damm@gmail.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
---
include/linux/mmc/sh_mmcif.h | 9 +++------
1 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/include/linux/mmc/sh_mmcif.h b/include/linux/mmc/sh_mmcif.h
index f216a88..519a2cd 100644
--- a/include/linux/mmc/sh_mmcif.h
+++ b/include/linux/mmc/sh_mmcif.h
@@ -87,7 +87,7 @@ struct sh_mmcif_plat_data {
/* CE_VERSION */
#define SOFT_RST_ON (1 << 31)
-#define SOFT_RST_OFF ~SOFT_RST_ON
+#define SOFT_RST_OFF 0
static inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
{
@@ -175,12 +175,9 @@ static inline int sh_mmcif_boot_do_read(void __iomem *base,
static inline void sh_mmcif_boot_init(void __iomem *base)
{
- unsigned long tmp;
-
/* reset */
- tmp = sh_mmcif_readl(base, MMCIF_CE_VERSION);
- sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp | SOFT_RST_ON);
- sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp & SOFT_RST_OFF);
+ sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON);
+ sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF);
/* byte swap */
sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
--
1.7.2.3
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 3/3] sh, mmc: Use defines when setting CE_CLK_CTRL
2010-11-26 23:02 [PATCH 1/3] sh, mmc: Make mmcif_update_progress static inline Simon Horman
2010-11-26 23:02 ` [PATCH 2/3] mmc, sh: Correct value for reset Simon Horman
@ 2010-11-26 23:02 ` Simon Horman
2010-11-27 0:01 ` Simon Horman
2010-11-29 3:55 ` [PATCH 1/3] sh, mmc: Make mmcif_update_progress static inline Paul Mundt
2 siblings, 1 reply; 8+ messages in thread
From: Simon Horman @ 2010-11-26 23:02 UTC (permalink / raw)
To: linux-mmc, linux-sh
Cc: Yusuke Goda, Magnus Damm, Kuninori Morimoto, Chris Ball,
Paul Mundt, Simon Horman
The 16-19th bits of CE_CLK_CTRL set the
MMC clock frequency.
Cc: Yusuke Goda <yusuke.goda.sx@renesas.com>
Cc: Magnus Damm <magnus.damm@gmail.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
---
include/linux/mmc/sh_mmcif.h | 19 +++++++++++--------
1 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/include/linux/mmc/sh_mmcif.h b/include/linux/mmc/sh_mmcif.h
index 519a2cd..adf9dba 100644
--- a/include/linux/mmc/sh_mmcif.h
+++ b/include/linux/mmc/sh_mmcif.h
@@ -77,6 +77,9 @@ struct sh_mmcif_plat_data {
#define CLK_ENABLE (1 << 24) /* 1: output mmc clock */
#define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
#define CLK_SUP_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
+#define CLKDIV_4 (1<<16) /* mmc clock frequency.
+ * n: bus clock/(2^(n+1)) */
+#define CLKDIV_256 (7<<16) /* mmc clock frequency. (see above) */
#define SRSPTO_256 ((1 << 13) | (0 << 12)) /* resp timeout */
#define SRBSYTO_29 ((1 << 11) | (1 << 10) | \
(1 << 9) | (1 << 8)) /* resp busy timeout */
@@ -185,14 +188,10 @@ static inline void sh_mmcif_boot_init(void __iomem *base)
/* Set block size in MMCIF hardware */
sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);
- /* Enable the clock, set it to Bus clock/256 (about 325Khz).
- * It is unclear where 0x70000 comes from or if it is even needed.
- * It is there for byte-compatibility with code that is known to
- * work.
- */
+ /* Enable the clock, set it to Bus clock/256 (about 325Khz). */
sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
- CLK_ENABLE | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 |
- SCCSTO_29 | 0x70000);
+ CLK_ENABLE | CLKDIV_256 | SRSPTO_256 |
+ SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
/* CMD0 */
sh_mmcif_boot_cmd(base, 0x00000040, 0);
@@ -216,8 +215,12 @@ static inline void sh_mmcif_boot_slurp(void __iomem *base,
{
unsigned long tmp;
+ return;
+
/* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
- sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01012fff);
+ sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
+ CLK_ENABLE | CLKDIV_4 | SRSPTO_256 |
+ SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
/* CMD9 - Get CSD */
sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);
--
1.7.2.3
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 3/3] sh, mmc: Use defines when setting CE_CLK_CTRL
2010-11-26 23:02 ` [PATCH 3/3] sh, mmc: Use defines when setting CE_CLK_CTRL Simon Horman
@ 2010-11-27 0:01 ` Simon Horman
2010-11-27 0:11 ` [PATCH 3/3 v2] " Simon Horman
0 siblings, 1 reply; 8+ messages in thread
From: Simon Horman @ 2010-11-27 0:01 UTC (permalink / raw)
To: linux-mmc, linux-sh
Cc: Yusuke Goda, Magnus Damm, Kuninori Morimoto, Chris Ball,
Paul Mundt
On Sat, Nov 27, 2010 at 08:02:59AM +0900, Simon Horman wrote:
> The 16-19th bits of CE_CLK_CTRL set the
> MMC clock frequency.
>
> Cc: Yusuke Goda <yusuke.goda.sx@renesas.com>
> Cc: Magnus Damm <magnus.damm@gmail.com>
> Signed-off-by: Simon Horman <horms@verge.net.au>
> ---
> include/linux/mmc/sh_mmcif.h | 19 +++++++++++--------
> 1 files changed, 11 insertions(+), 8 deletions(-)
>
> diff --git a/include/linux/mmc/sh_mmcif.h b/include/linux/mmc/sh_mmcif.h
> index 519a2cd..adf9dba 100644
> --- a/include/linux/mmc/sh_mmcif.h
> +++ b/include/linux/mmc/sh_mmcif.h
> @@ -77,6 +77,9 @@ struct sh_mmcif_plat_data {
> #define CLK_ENABLE (1 << 24) /* 1: output mmc clock */
> #define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
> #define CLK_SUP_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
> +#define CLKDIV_4 (1<<16) /* mmc clock frequency.
> + * n: bus clock/(2^(n+1)) */
> +#define CLKDIV_256 (7<<16) /* mmc clock frequency. (see above) */
> #define SRSPTO_256 ((1 << 13) | (0 << 12)) /* resp timeout */
> #define SRBSYTO_29 ((1 << 11) | (1 << 10) | \
> (1 << 9) | (1 << 8)) /* resp busy timeout */
> @@ -185,14 +188,10 @@ static inline void sh_mmcif_boot_init(void __iomem *base)
> /* Set block size in MMCIF hardware */
> sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);
>
> - /* Enable the clock, set it to Bus clock/256 (about 325Khz).
> - * It is unclear where 0x70000 comes from or if it is even needed.
> - * It is there for byte-compatibility with code that is known to
> - * work.
> - */
> + /* Enable the clock, set it to Bus clock/256 (about 325Khz). */
> sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
> - CLK_ENABLE | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 |
> - SCCSTO_29 | 0x70000);
> + CLK_ENABLE | CLKDIV_256 | SRSPTO_256 |
> + SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
>
> /* CMD0 */
> sh_mmcif_boot_cmd(base, 0x00000040, 0);
> @@ -216,8 +215,12 @@ static inline void sh_mmcif_boot_slurp(void __iomem *base,
> {
> unsigned long tmp;
>
> + return;
Sorry, this line is bogus and crept in as part of some
other testing. I will repost this patch.
> +
> /* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
> - sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01012fff);
> + sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
> + CLK_ENABLE | CLKDIV_4 | SRSPTO_256 |
> + SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
>
> /* CMD9 - Get CSD */
> sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);
> --
> 1.7.2.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
--
Simon Horman simon@horms.net
Horms Solutions Ltd. www.horms.net
1701 Emblem Court Akashicho, 6-13 Akashicho, Chuo-ku, Tokyo 104-0044, Japan
Phone: +81 3 6365 5977 Fax: +81 3 6673 4268
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 3/3 v2] sh, mmc: Use defines when setting CE_CLK_CTRL
2010-11-27 0:01 ` Simon Horman
@ 2010-11-27 0:11 ` Simon Horman
2010-11-27 11:54 ` Michał Mirosław
0 siblings, 1 reply; 8+ messages in thread
From: Simon Horman @ 2010-11-27 0:11 UTC (permalink / raw)
To: linux-mmc, linux-sh
Cc: Yusuke Goda, Magnus Damm, Kuninori Morimoto, Chris Ball,
Paul Mundt
The 16-19th bits of CE_CLK_CTRL set the
MMC clock frequency.
Cc: Yusuke Goda <yusuke.goda.sx@renesas.com>
Cc: Magnus Damm <magnus.damm@gmail.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
---
include/linux/mmc/sh_mmcif.h | 17 +++++++++--------
1 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/include/linux/mmc/sh_mmcif.h b/include/linux/mmc/sh_mmcif.h
index 519a2cd..44fc534 100644
--- a/include/linux/mmc/sh_mmcif.h
+++ b/include/linux/mmc/sh_mmcif.h
@@ -77,6 +77,9 @@ struct sh_mmcif_plat_data {
#define CLK_ENABLE (1 << 24) /* 1: output mmc clock */
#define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
#define CLK_SUP_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
+#define CLKDIV_4 (1<<16) /* mmc clock frequency.
+ * n: bus clock/(2^(n+1)) */
+#define CLKDIV_256 (7<<16) /* mmc clock frequency. (see above) */
#define SRSPTO_256 ((1 << 13) | (0 << 12)) /* resp timeout */
#define SRBSYTO_29 ((1 << 11) | (1 << 10) | \
(1 << 9) | (1 << 8)) /* resp busy timeout */
@@ -185,14 +188,10 @@ static inline void sh_mmcif_boot_init(void __iomem *base)
/* Set block size in MMCIF hardware */
sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);
- /* Enable the clock, set it to Bus clock/256 (about 325Khz).
- * It is unclear where 0x70000 comes from or if it is even needed.
- * It is there for byte-compatibility with code that is known to
- * work.
- */
+ /* Enable the clock, set it to Bus clock/256 (about 325Khz). */
sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
- CLK_ENABLE | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 |
- SCCSTO_29 | 0x70000);
+ CLK_ENABLE | CLKDIV_256 | SRSPTO_256 |
+ SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
/* CMD0 */
sh_mmcif_boot_cmd(base, 0x00000040, 0);
@@ -217,7 +216,9 @@ static inline void sh_mmcif_boot_slurp(void __iomem *base,
unsigned long tmp;
/* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
- sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01012fff);
+ sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
+ CLK_ENABLE | CLKDIV_4 | SRSPTO_256 |
+ SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
/* CMD9 - Get CSD */
sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);
--
1.7.2.3
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 3/3 v2] sh, mmc: Use defines when setting CE_CLK_CTRL
2010-11-27 0:11 ` [PATCH 3/3 v2] " Simon Horman
@ 2010-11-27 11:54 ` Michał Mirosław
2010-11-27 21:17 ` Simon Horman
0 siblings, 1 reply; 8+ messages in thread
From: Michał Mirosław @ 2010-11-27 11:54 UTC (permalink / raw)
To: Simon Horman
Cc: linux-mmc, linux-sh, Yusuke Goda, Magnus Damm, Kuninori Morimoto,
Chris Ball, Paul Mundt
2010/11/27 Simon Horman <horms@verge.net.au>:
> The 16-19th bits of CE_CLK_CTRL set the
> MMC clock frequency.
>
> Cc: Yusuke Goda <yusuke.goda.sx@renesas.com>
> Cc: Magnus Damm <magnus.damm@gmail.com>
> Signed-off-by: Simon Horman <horms@verge.net.au>
> ---
> include/linux/mmc/sh_mmcif.h | 17 +++++++++--------
> 1 files changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/include/linux/mmc/sh_mmcif.h b/include/linux/mmc/sh_mmcif.h
> index 519a2cd..44fc534 100644
> --- a/include/linux/mmc/sh_mmcif.h
> +++ b/include/linux/mmc/sh_mmcif.h
> @@ -77,6 +77,9 @@ struct sh_mmcif_plat_data {
> #define CLK_ENABLE (1 << 24) /* 1: output mmc clock */
> #define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
> #define CLK_SUP_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
> +#define CLKDIV_4 (1<<16) /* mmc clock frequency.
> + * n: bus clock/(2^(n+1)) */
> +#define CLKDIV_256 (7<<16) /* mmc clock frequency. (see above) */
> #define SRSPTO_256 ((1 << 13) | (0 << 12)) /* resp timeout */
> #define SRBSYTO_29 ((1 << 11) | (1 << 10) | \
> (1 << 9) | (1 << 8)) /* resp busy timeout */
[...]
Maybe zero is a valid value here meaning CLKDIV = 2.
Best Regards,
Michał Mirosław
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 3/3 v2] sh, mmc: Use defines when setting CE_CLK_CTRL
2010-11-27 11:54 ` Michał Mirosław
@ 2010-11-27 21:17 ` Simon Horman
0 siblings, 0 replies; 8+ messages in thread
From: Simon Horman @ 2010-11-27 21:17 UTC (permalink / raw)
To: Michał Mirosław
Cc: linux-mmc, linux-sh, Yusuke Goda, Magnus Damm, Kuninori Morimoto,
Chris Ball, Paul Mundt
On Sat, Nov 27, 2010 at 12:54:41PM +0100, Michał Mirosław wrote:
> 2010/11/27 Simon Horman <horms@verge.net.au>:
> > The 16-19th bits of CE_CLK_CTRL set the
> > MMC clock frequency.
> >
> > Cc: Yusuke Goda <yusuke.goda.sx@renesas.com>
> > Cc: Magnus Damm <magnus.damm@gmail.com>
> > Signed-off-by: Simon Horman <horms@verge.net.au>
> > ---
> > include/linux/mmc/sh_mmcif.h | 17 +++++++++--------
> > 1 files changed, 9 insertions(+), 8 deletions(-)
> >
> > diff --git a/include/linux/mmc/sh_mmcif.h b/include/linux/mmc/sh_mmcif.h
> > index 519a2cd..44fc534 100644
> > --- a/include/linux/mmc/sh_mmcif.h
> > +++ b/include/linux/mmc/sh_mmcif.h
> > @@ -77,6 +77,9 @@ struct sh_mmcif_plat_data {
> > #define CLK_ENABLE (1 << 24) /* 1: output mmc clock */
> > #define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
> > #define CLK_SUP_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
> > +#define CLKDIV_4 (1<<16) /* mmc clock frequency.
> > + * n: bus clock/(2^(n+1)) */
> > +#define CLKDIV_256 (7<<16) /* mmc clock frequency. (see above) */
> > #define SRSPTO_256 ((1 << 13) | (0 << 12)) /* resp timeout */
> > #define SRBSYTO_29 ((1 << 11) | (1 << 10) | \
> > (1 << 9) | (1 << 8)) /* resp busy timeout */
> [...]
>
> Maybe zero is a valid value here meaning CLKDIV = 2.
Hi Michał,
Yes, it is. I intended to provide defines only for values that are used.
But I can provide all the valid values (there are only 9) it that
makes thing clearer. Or perhaps change the comment to:
/* CLKDIV_n
* mmc clock frequency.
* n: bus clock/(2^(m+1))
* where 0 <= m <= 8 */
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] sh, mmc: Make mmcif_update_progress static inline
2010-11-26 23:02 [PATCH 1/3] sh, mmc: Make mmcif_update_progress static inline Simon Horman
2010-11-26 23:02 ` [PATCH 2/3] mmc, sh: Correct value for reset Simon Horman
2010-11-26 23:02 ` [PATCH 3/3] sh, mmc: Use defines when setting CE_CLK_CTRL Simon Horman
@ 2010-11-29 3:55 ` Paul Mundt
2 siblings, 0 replies; 8+ messages in thread
From: Paul Mundt @ 2010-11-29 3:55 UTC (permalink / raw)
To: Simon Horman
Cc: linux-mmc, linux-sh, Yusuke Goda, Magnus Damm, Kuninori Morimoto,
Chris Ball
On Sat, Nov 27, 2010 at 08:02:57AM +0900, Simon Horman wrote:
> extern inline doesn't make much sense
>
> Cc: Yusuke Goda <yusuke.goda.sx@renesas.com>
> Cc: Magnus Damm <magnus.damm@gmail.com>
> Signed-off-by: Simon Horman <horms@verge.net.au>
On Sat, Nov 27, 2010 at 08:02:58AM +0900, Simon Horman wrote:
> This resolves a regression that I introduced in
> "mmc, sh: Move constants to sh_mmcif.h". Having
> examined the manual and tested the code on an AP4EVB board
> it seems that the correct sequence is.
>
> 1) Write 1 to bit 31 and zeros to all other bits
> 2) Write zero to all bits
>
> Cc: Yusuke Goda <yusuke.goda.sx@renesas.com>
> Cc: Magnus Damm <magnus.damm@gmail.com>
> Signed-off-by: Simon Horman <horms@verge.net.au>
On Sat, Nov 27, 2010 at 09:11:55AM +0900, Simon Horman wrote:
> The 16-19th bits of CE_CLK_CTRL set the
> MMC clock frequency.
>
> Cc: Yusuke Goda <yusuke.goda.sx@renesas.com>
> Cc: Magnus Damm <magnus.damm@gmail.com>
> Signed-off-by: Simon Horman <horms@verge.net.au>
Applied, thanks.
^ permalink raw reply [flat|nested] 8+ messages in thread