[PATCH 0/6] workaround for FSL's eSDHC controller

[PATCH 0/6] workaround for FSL's eSDHC controller

[r66093]

From: Jerry Huang <Chang-Ming.Huang@freescale.com>

The below patches are the workaround for FSL's eSDHC controller.

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>

[PATCH 1/6] ESDHC: add PIO mode support

[r66093]

From: Jerry Huang <Chang-Ming.Huang@freescale.com>

For some FSL ESDHC controller(e.g. P2020E, Rev1.0), the SDHC can not work on
DMA mode because of the hardware bug, so we set a broken dma flag and use
PIO mode.

Signed-off-by: Gao Guanhua <B22826@freescale.com>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
---
 drivers/mmc/host/sdhci-pltfm.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
index a9e12ea..2a77435 100644
--- a/drivers/mmc/host/sdhci-pltfm.c
+++ b/drivers/mmc/host/sdhci-pltfm.c
@@ -2,7 +2,7 @@
  * sdhci-pltfm.c Support for SDHCI platform devices
  * Copyright (c) 2009 Intel Corporation
  *
- * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ * Copyright (c) 2007, 2011 Freescale Semiconductor, Inc.
  * Copyright (c) 2009 MontaVista Software, Inc.
  *
  * Authors: Xiaobo Xie <X.Xie@freescale.com>
@@ -71,6 +71,9 @@ void sdhci_get_of_property(struct platform_device *pdev)
 		if (sdhci_of_wp_inverted(np))
 			host->quirks |= SDHCI_QUIRK_INVERTED_WRITE_PROTECT;
 
+		if (of_get_property(np, "sdhci,dma-broken", NULL))
+			host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
+
 		clk = of_get_property(np, "clock-frequency", &size);
 		if (clk && size == sizeof(*clk) && *clk)
 			pltfm_host->clock = be32_to_cpup(clk);
-- 
1.7.5.4

[PATCH 2/6] SDHCI: AHB2MAG IRQ bypass hardware workaround

[r66093]

From: Jerry Huang <Chang-Ming.Huang@freescale.com>

For Fsl eSDHC controller, the bit DCR[DMA__AHB2MAG_IRQ_BYPASS] cannot be
set automatically, when SoC reset, therefore, we need to set this bit manually.

Signed-off-by: Gao Guanhua <B22826@freescale.com>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
---
 drivers/mmc/host/sdhci-esdhc.h    |    1 +
 drivers/mmc/host/sdhci-of-esdhc.c |    7 +++++++
 drivers/mmc/host/sdhci-pltfm.c    |    3 +++
 drivers/mmc/host/sdhci.c          |    4 ++++
 drivers/mmc/host/sdhci.h          |    1 +
 include/linux/mmc/sdhci.h         |    2 ++
 6 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/drivers/mmc/host/sdhci-esdhc.h b/drivers/mmc/host/sdhci-esdhc.h
index c3b08f1..7cbaffe 100644
--- a/drivers/mmc/host/sdhci-esdhc.h
+++ b/drivers/mmc/host/sdhci-esdhc.h
@@ -39,6 +39,7 @@
 /* OF-specific */
 #define ESDHC_DMA_SYSCTL	0x40c
 #define ESDHC_DMA_SNOOP		0x00000040
+#define ESDHC_AHB2MAG_IRQ_BYPASS	0x20
 
 #define ESDHC_HOST_CONTROL_RES	0x05
 
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
index 7d5ae82..413ded5 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -68,6 +68,12 @@ static int esdhc_of_enable_dma(struct sdhci_host *host)
 	return 0;
 }
 
+static int esdhc_of_enable_irq_bypass(struct sdhci_host *host)
+{
+	setbits32(host->ioaddr + ESDHC_DMA_SYSCTL, ESDHC_AHB2MAG_IRQ_BYPASS);
+	return 0;
+}
+
 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
 {
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -116,6 +122,7 @@ static struct sdhci_ops sdhci_esdhc_ops = {
 	.get_max_clock = esdhc_of_get_max_clock,
 	.get_min_clock = esdhc_of_get_min_clock,
 	.get_cd = esdhc_of_get_cd,
+	.enable_irq_bypass = esdhc_of_enable_irq_bypass,
 };
 
 static struct sdhci_pltfm_data sdhci_esdhc_pdata = {
diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
index 2a77435..de182c6 100644
--- a/drivers/mmc/host/sdhci-pltfm.c
+++ b/drivers/mmc/host/sdhci-pltfm.c
@@ -74,6 +74,9 @@ void sdhci_get_of_property(struct platform_device *pdev)
 		if (of_get_property(np, "sdhci,dma-broken", NULL))
 			host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
 
+		if (of_get_property(np, "sdhci,ahb2mag-irq-bypass", NULL))
+			host->quirks2 |= SDHCI_QUIRK2_SET_AHB2MAG_IRQ_BYPASS;
+
 		clk = of_get_property(np, "clock-frequency", &size);
 		if (clk && size == sizeof(*clk) && *clk)
 			pltfm_host->clock = be32_to_cpup(clk);
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index fbe2f46..ae52ab9 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -226,6 +226,10 @@ static void sdhci_init(struct sdhci_host *host, int soft)
 	else
 		sdhci_reset(host, SDHCI_RESET_ALL);
 
+	if (host->quirks2 & SDHCI_QUIRK2_SET_AHB2MAG_IRQ_BYPASS)
+		if (host->ops->enable_irq_bypass)
+			host->ops->enable_irq_bypass(host);
+
 	sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
 		SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 		SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 82f4d27..1326557 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -263,6 +263,7 @@ struct sdhci_ops {
 	void	(*set_clock)(struct sdhci_host *host, unsigned int clock);
 
 	int		(*get_cd)(struct sdhci_host *host);
+	int		(*enable_irq_bypass)(struct sdhci_host *host);
 	int		(*enable_dma)(struct sdhci_host *host);
 	unsigned int	(*get_max_clock)(struct sdhci_host *host);
 	unsigned int	(*get_min_clock)(struct sdhci_host *host);
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index e4b6935..1dbe22b 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -91,6 +91,8 @@ struct sdhci_host {
 	unsigned int quirks2;	/* More deviations from spec. */
 
 #define SDHCI_QUIRK2_OWN_CARD_DETECTION			(1<<0)
+/* Controller cannot set DCR[DMA__AHB2MAG_IRQ_BYPASS] automatically */
+#define SDHCI_QUIRK2_SET_AHB2MAG_IRQ_BYPASS		(1<<1)
 
 	int irq;		/* Device IRQ */
 	void __iomem *ioaddr;	/* Mapped address */
-- 
1.7.5.4

[PATCH 3/6] ESDHC: set the timeout to the max value

[r66093]

From: Jerry Huang <Chang-Ming.Huang@freescale.com>

When access the card on some FSL platform board (e.g p2020, p1010, mpc8536),
the following error is reported with the timeout value calculated:

mmc0: Got data interrupt 0x00000020 even though no data operation was
in progress.
mmc0: Got data interrupt 0x00000020 even though no data operation was
in progress.

So we skip the calculation of timeout and use the max value to fix it.

Signed-off-by: Gao Guanhua <B22826@freescale.com>
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
---
 drivers/mmc/host/sdhci-pltfm.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
index 5417d84..c4ec8bd 100644
--- a/drivers/mmc/host/sdhci-pltfm.c
+++ b/drivers/mmc/host/sdhci-pltfm.c
@@ -74,6 +74,9 @@ void sdhci_get_of_property(struct platform_device *pdev)
 		if (of_get_property(np, "sdhci,dma-broken", NULL))
 			host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
 
+		if (of_get_property(np, "sdhci,adjust-timeout", NULL))
+			host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
+
 		if (of_get_property(np, "sdhci,ahb2mag-irq-bypass", NULL))
 			host->quirks2 |= SDHCI_QUIRK2_SET_AHB2MAG_IRQ_BYPASS;
 
-- 
1.7.5.4

[PATCH 4/6] ESDHC: Power management for ESDHC

[r66093]

From: Jerry Huang <Chang-Ming.Huang@freescale.com>

For FSL ESDHC controllor, when enter the sleep, the controller will power off,
therefore the register will lost its valuse, and driver should save value of
register during suspend and used during resume.

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Jiang Yutang <b14898@freescale.com>
---
 drivers/mmc/host/sdhci-pltfm.c |   21 +++++++++++++++++++--
 1 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
index c4ec8bd..e39bb13 100644
--- a/drivers/mmc/host/sdhci-pltfm.c
+++ b/drivers/mmc/host/sdhci-pltfm.c
@@ -53,6 +53,10 @@ static bool sdhci_of_wp_inverted(struct device_node *np)
 #endif /* CONFIG_PPC */
 }
 
+#ifdef CONFIG_PM
+static int sdhc_pmsaveproctlreg;
+static u32 esdhc_proctl;
+#endif
 void sdhci_get_of_property(struct platform_device *pdev)
 {
 	struct device_node *np = pdev->dev.of_node;
@@ -79,7 +83,10 @@ void sdhci_get_of_property(struct platform_device *pdev)
 
 		if (of_get_property(np, "sdhci,ahb2mag-irq-bypass", NULL))
 			host->quirks2 |= SDHCI_QUIRK2_SET_AHB2MAG_IRQ_BYPASS;
-
+#ifdef CONFIG_PM
+		if (of_get_property(np, "pmsaveproctlreg", NULL))
+			sdhc_pmsaveproctlreg = 1;
+#endif
 		clk = of_get_property(np, "clock-frequency", &size);
 		if (clk && size == sizeof(*clk) && *clk)
 			pltfm_host->clock = be32_to_cpup(clk);
@@ -207,15 +214,25 @@ int sdhci_pltfm_suspend(struct platform_device *dev, pm_message_t state)
 {
 	struct sdhci_host *host = platform_get_drvdata(dev);
 
+	if (sdhc_pmsaveproctlreg == 1)
+		esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL);
+
 	return sdhci_suspend_host(host, state);
 }
 EXPORT_SYMBOL_GPL(sdhci_pltfm_suspend);
 
 int sdhci_pltfm_resume(struct platform_device *dev)
 {
+	int ret;
 	struct sdhci_host *host = platform_get_drvdata(dev);
 
-	return sdhci_resume_host(host);
+	 host->ops->enable_dma(host);
+
+	ret = mmc_resume_host(host->mmc);
+	if (sdhc_pmsaveproctlreg == 1)
+		sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
+
+	return ret;
 }
 EXPORT_SYMBOL_GPL(sdhci_pltfm_resume);
 #endif	/* CONFIG_PM */
-- 
1.7.5.4

[PATCH 5/6] ESDHC: Workaround for data crc error on p1010rdb

[r66093]

From: Jerry Huang <Chang-Ming.Huang@freescale.com>

SD card read was failing (data crc error)on some cards at
maximum possible frequency on P1010(CCB frequency set to 400MHz).
Some clock deviations are also observed at this frequency.
Hence reduced the mmc clock freq.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Singed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
---
 drivers/mmc/host/sdhci-esdhc.h |    9 ++++++++-
 drivers/mmc/host/sdhci-pltfm.c |    3 +++
 include/linux/mmc/sdhci.h      |    2 ++
 3 files changed, 13 insertions(+), 1 deletions(-)

diff --git a/drivers/mmc/host/sdhci-esdhc.h b/drivers/mmc/host/sdhci-esdhc.h
index 7cbaffe..e0d3029 100644
--- a/drivers/mmc/host/sdhci-esdhc.h
+++ b/drivers/mmc/host/sdhci-esdhc.h
@@ -1,7 +1,7 @@
 /*
  * Freescale eSDHC controller driver generics for OF and pltfm.
  *
- * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ * Copyright (c) 2007,2011 Freescale Semiconductor, Inc.
  * Copyright (c) 2009 MontaVista Software, Inc.
  * Copyright (c) 2010 Pengutronix e.K.
  *   Author: Wolfram Sang <w.sang@pengutronix.de>
@@ -57,6 +57,13 @@ static inline void esdhc_set_clock(struct sdhci_host *host, unsigned int clock)
 	if (clock == 0)
 		goto out;
 
+	if (host->quirks2 & SDHCI_QUIRK2_RELAX_FREQ) {
+		if (clock > 20000000)
+			clock -= 5000000;
+		if (clock > 40000000)
+			clock -= 5000000;
+	}
+
 	while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
 		pre_div *= 2;
 
diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
index e39bb13..8ece860 100644
--- a/drivers/mmc/host/sdhci-pltfm.c
+++ b/drivers/mmc/host/sdhci-pltfm.c
@@ -83,6 +83,9 @@ void sdhci_get_of_property(struct platform_device *pdev)
 
 		if (of_get_property(np, "sdhci,ahb2mag-irq-bypass", NULL))
 			host->quirks2 |= SDHCI_QUIRK2_SET_AHB2MAG_IRQ_BYPASS;
+
+		if (of_get_property(np, "sdhci,relax-freq", NULL))
+			host->quirks2 |= SDHCI_QUIRK2_RELAX_FREQ;
 #ifdef CONFIG_PM
 		if (of_get_property(np, "pmsaveproctlreg", NULL))
 			sdhc_pmsaveproctlreg = 1;
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index 1dbe22b..b5f9559 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -93,6 +93,8 @@ struct sdhci_host {
 #define SDHCI_QUIRK2_OWN_CARD_DETECTION			(1<<0)
 /* Controller cannot set DCR[DMA__AHB2MAG_IRQ_BYPASS] automatically */
 #define SDHCI_QUIRK2_SET_AHB2MAG_IRQ_BYPASS		(1<<1)
+/* Controller operates the cards at reduced frequency */
+#define SDHCI_QUIRK2_RELAX_FREQ				(1<<2)
 
 	int irq;		/* Device IRQ */
 	void __iomem *ioaddr;	/* Mapped address */
-- 
1.7.5.4

[PATCH 6/6] ESDHC: Fix DMA errors in kernel booting on P1010

[r66093]

From: Jerry Huang <Chang-Ming.Huang@freescale.com>

When linux is booted with DMA mode enabled in esdhc module on P1010,
there were following errors:

mmc0: ADMA error
mmc0: error -5 whilst initialising SD card

It is because FSL ESDHC controller has different bit setting for PROCTL
register, when kernel sets Power Control Register by method for standard
SD Host Specification, it would overwritten FSL ESDHC PROCTL[DMAS];
when it set Host Control Registers[DMAS], it sets PROCTL[EMODE] and
PROCTL[D3CD]. These operations will set bad bits for PROCTL Register
on FSL ESDHC Controller and cause errors, so this patch will make esdhc
driver access FSL PROCTL Register according to block guide instead of
standard SD Host Specification.

For some FSL chips, such as MPC8536/P2020, PROCTL[VOLT_SEL] and PROCTL[DMAS]
bits are reserved and even if they are set to wrong bits there is no error.
But considering that all FSL ESDHC Controller register map is not fully
compliant to standard SD Host Specification, we put the patch to all of
FSL ESDHC Controllers.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
---
 drivers/mmc/host/sdhci-pltfm.c |    4 ++
 drivers/mmc/host/sdhci.c       |   61 ++++++++++++++++++++++++++++++++-------
 include/linux/mmc/sdhci.h      |    2 +
 3 files changed, 56 insertions(+), 11 deletions(-)

diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
index 8ece860..103abe9 100644
--- a/drivers/mmc/host/sdhci-pltfm.c
+++ b/drivers/mmc/host/sdhci-pltfm.c
@@ -86,6 +86,10 @@ void sdhci_get_of_property(struct platform_device *pdev)
 
 		if (of_get_property(np, "sdhci,relax-freq", NULL))
 			host->quirks2 |= SDHCI_QUIRK2_RELAX_FREQ;
+
+		if (of_device_is_compatible(np, "fsl,esdhc"))
+			host->quirks2 |= SDHCI_QUIRK2_QORIQ_PROCTL_WEIRD;
+
 #ifdef CONFIG_PM
 		if (of_get_property(np, "pmsaveproctlreg", NULL))
 			sdhc_pmsaveproctlreg = 1;
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index ae52ab9..eccaaf4 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -837,14 +837,29 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 	 * is ADMA.
 	 */
 	if (host->version >= SDHCI_SPEC_200) {
-		ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
-		ctrl &= ~SDHCI_CTRL_DMA_MASK;
-		if ((host->flags & SDHCI_REQ_USE_DMA) &&
-			(host->flags & SDHCI_USE_ADMA))
-			ctrl |= SDHCI_CTRL_ADMA32;
-		else
-			ctrl |= SDHCI_CTRL_SDMA;
-		sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+		if (host->quirks2 & SDHCI_QUIRK2_QORIQ_PROCTL_WEIRD) {
+#define ESDHCI_PROCTL_DMAS_MASK		0x00000300
+#define ESDHCI_PROCTL_ADMA32		0x00000200
+#define ESDHCI_PROCTL_SDMA		0x00000000
+			u32 ctrl;
+			ctrl = sdhci_readl(host, SDHCI_HOST_CONTROL);
+			ctrl &= ~ESDHCI_PROCTL_DMAS_MASK;
+			if ((host->flags & SDHCI_REQ_USE_DMA) &&
+				(host->flags & SDHCI_USE_ADMA))
+				ctrl |= ESDHCI_PROCTL_ADMA32;
+			else
+				ctrl |= ESDHCI_PROCTL_SDMA;
+			sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL);
+		} else {
+			ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+			ctrl &= ~SDHCI_CTRL_DMA_MASK;
+			if ((host->flags & SDHCI_REQ_USE_DMA) &&
+				(host->flags & SDHCI_USE_ADMA))
+				ctrl |= SDHCI_CTRL_ADMA32;
+			else
+				ctrl |= SDHCI_CTRL_SDMA;
+			sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+		}
 	}
 
 	if (!(host->flags & SDHCI_REQ_USE_DMA)) {
@@ -1170,17 +1185,29 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 	u8 pwr = 0;
 
 	if (power != (unsigned short)-1) {
+#define	ESDHCI_FSL_POWER_MASK	0x40
+#define	ESDHCI_FSL_POWER_180	0x00
+#define	ESDHCI_FSL_POWER_300	0x40
 		switch (1 << power) {
 		case MMC_VDD_165_195:
-			pwr = SDHCI_POWER_180;
+			if (host->quirks2 & SDHCI_QUIRK2_QORIQ_PROCTL_WEIRD)
+				pwr = ESDHCI_FSL_POWER_180;
+			else
+				pwr = SDHCI_POWER_180;
 			break;
 		case MMC_VDD_29_30:
 		case MMC_VDD_30_31:
-			pwr = SDHCI_POWER_300;
+			if (host->quirks2 & SDHCI_QUIRK2_QORIQ_PROCTL_WEIRD)
+				pwr = ESDHCI_FSL_POWER_300;
+			else
+				pwr = SDHCI_POWER_300;
 			break;
 		case MMC_VDD_32_33:
 		case MMC_VDD_33_34:
-			pwr = SDHCI_POWER_330;
+			if (host->quirks2 & SDHCI_QUIRK2_QORIQ_PROCTL_WEIRD)
+				pwr = ESDHCI_FSL_POWER_300;
+			else
+				pwr = SDHCI_POWER_330;
 			break;
 		default:
 			BUG();
@@ -1190,6 +1217,18 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 	if (host->pwr == pwr)
 		return;
 
+	/* Now FSL ESDHC Controller has no Bus Power bit,
+	 * and PROCTL[21] bit is for voltage selection */
+	if (host->quirks2 & SDHCI_QUIRK2_QORIQ_PROCTL_WEIRD) {
+		u8 volt = 0;
+		volt = sdhci_readb(host, SDHCI_POWER_CONTROL);
+		volt &= ~ESDHCI_FSL_POWER_MASK;
+		volt |= pwr;
+		sdhci_writeb(host, volt, SDHCI_POWER_CONTROL);
+
+		return;
+	}
+
 	host->pwr = pwr;
 
 	if (pwr == 0) {
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index b5f9559..e1331d6 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -95,6 +95,8 @@ struct sdhci_host {
 #define SDHCI_QUIRK2_SET_AHB2MAG_IRQ_BYPASS		(1<<1)
 /* Controller operates the cards at reduced frequency */
 #define SDHCI_QUIRK2_RELAX_FREQ				(1<<2)
+/* Controller has weird bit setting for Protocol Control Register */
+#define SDHCI_QUIRK2_QORIQ_PROCTL_WEIRD			(1<<3)
 
 	int irq;		/* Device IRQ */
 	void __iomem *ioaddr;	/* Mapped address */
-- 
1.7.5.4

Re: [PATCH 1/6] ESDHC: add PIO mode support

[Wolfram Sang]

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On Wed, Dec 14, 2011 at 10:19:37AM +0800, r66093@freescale.com wrote:
> From: Jerry Huang <Chang-Ming.Huang@freescale.com>
> 
> For some FSL ESDHC controller(e.g. P2020E, Rev1.0), the SDHC can not work on
> DMA mode because of the hardware bug, so we set a broken dma flag and use
> PIO mode.
> 
> Signed-off-by: Gao Guanhua <B22826@freescale.com>
> Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>

NACK for the series

1) If you introduce a new property you always have to document the binding
which is missing. But you don't need to write it because...

2) ... the aproach seems wrong to me. The quirks should be set depending
on the compatible entry, e.g. if compatible == "this_controller" then
quirks |= whatever_needed. Or?

   Wolfram

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

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RE: [PATCH 1/6] ESDHC: add PIO mode support

[Huang Changming-R66093]

> -----Original Message-----
> From: linux-mmc-owner@vger.kernel.org [mailto:linux-mmc-
> owner@vger.kernel.org] On Behalf Of Wolfram Sang
> Sent: Wednesday, December 14, 2011 3:04 PM
> To: Huang Changming-R66093
> Cc: linux-mmc@vger.kernel.org; Huang Changming-R66093; Gao Guanhua-B22826
> Subject: Re: [PATCH 1/6] ESDHC: add PIO mode support
> 
> On Wed, Dec 14, 2011 at 10:19:37AM +0800, r66093@freescale.com wrote:
> > From: Jerry Huang <Chang-Ming.Huang@freescale.com>
> >
> > For some FSL ESDHC controller(e.g. P2020E, Rev1.0), the SDHC can not
> > work on DMA mode because of the hardware bug, so we set a broken dma
> > flag and use PIO mode.
> >
> > Signed-off-by: Gao Guanhua <B22826@freescale.com>
> > Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
> 
> NACK for the series
> 
> 1) If you introduce a new property you always have to document the
> binding which is missing. But you don't need to write it because...
I will document them.

> 2) ... the aproach seems wrong to me. The quirks should be set depending
> on the compatible entry, e.g. if compatible == "this_controller" then
> quirks |= whatever_needed. Or?
> 
The quirk will not be set only depending on the compatible entry, the property entry can be, too.

Re: [PATCH 1/6] ESDHC: add PIO mode support

[Wolfram Sang]

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> > 2) ... the aproach seems wrong to me. The quirks should be set depending on
> > the compatible entry, e.g. if compatible == "this_controller" then quirks
> > |= whatever_needed. Or?
> > 
> The quirk will not be set only depending on the compatible entry, the
> property entry can be, too.

Where is that needed? I don't see how they are board-specific.

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

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RE: [PATCH 1/6] ESDHC: add PIO mode support

[Huang Changming-R66093]

> -----Original Message-----
> From: Wolfram Sang [mailto:w.sang@pengutronix.de]
> Sent: Thursday, December 15, 2011 10:44 AM
> To: Huang Changming-R66093
> Cc: linux-mmc@vger.kernel.org; Gao Guanhua-B22826
> Subject: Re: [PATCH 1/6] ESDHC: add PIO mode support
> 
> > > 2) ... the aproach seems wrong to me. The quirks should be set
> > > depending on the compatible entry, e.g. if compatible ==
> > > "this_controller" then quirks
> > > |= whatever_needed. Or?
> > >
> > The quirk will not be set only depending on the compatible entry, the
> > property entry can be, too.
> 
> Where is that needed? I don't see how they are board-specific.
> 
Maybe you don't familiar with the Freescale's eSDHC controller.
For P2020E Rev1.0, the DMA can't work, we need the PIO mode.
For P2020E, P1010E, MPC8536, we can't use the timeout value calculated by driver, we need the max value.
For eSDHC, after suspending, the power of esdhc controller will shutdown, we need to save the value of some registers before suspending, wich will used to restore the context after resuming.
For eSDHC, the bit DCR[DMA__AHB2MAG_IRQ_BYPASS] can't be set automatically, so we need to set it manually
For P1010E, the eSDHC controller can't use the max possible frequency(e.g. SDHC 50MHz), so we need one workaround to make the SD work

Re: [PATCH 1/6] ESDHC: add PIO mode support

[Wolfram Sang]

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> For P2020E Rev1.0, the DMA can't work, we need the PIO mode.
> For P2020E, P1010E, MPC8536, we can't use the timeout value calculated by driver, we need the max value.
> For P1010E, the eSDHC controller can't use the max possible frequency(e.g. SDHC 50MHz), so we need one workaround to make the SD work

This is SoC specific, not board specific, so you could check for
"fsl,p2020-esdhc" for example. 1010 and 2020-rev1 would need proper compatibles
as well.

> For eSDHC, after suspending, the power of esdhc controller will shutdown, we need to save the value of some registers before suspending, wich will used to restore the context after resuming.
> For eSDHC, the bit DCR[DMA__AHB2MAG_IRQ_BYPASS] can't be set automatically, so we need to set it manually

If this is true for all revisions (be careful about the imx users), you don't
need properties, but could simply set it.

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

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RE: [PATCH 1/6] ESDHC: add PIO mode support

[Huang Changming-R66093]

> -----Original Message-----
> From: linux-mmc-owner@vger.kernel.org [mailto:linux-mmc-
> owner@vger.kernel.org] On Behalf Of Wolfram Sang
> Sent: Thursday, December 15, 2011 11:10 AM
> To: Huang Changming-R66093
> Cc: linux-mmc@vger.kernel.org; Gao Guanhua-B22826
> Subject: Re: [PATCH 1/6] ESDHC: add PIO mode support
> 
> > For P2020E Rev1.0, the DMA can't work, we need the PIO mode.
> > For P2020E, P1010E, MPC8536, we can't use the timeout value calculated
> by driver, we need the max value.
> > For P1010E, the eSDHC controller can't use the max possible
> frequency(e.g. SDHC 50MHz), so we need one workaround to make the SD work
> 
> This is SoC specific, not board specific, so you could check for
> "fsl,p2020-esdhc" for example. 1010 and 2020-rev1 would need proper
> compatibles
> as well.
I will think about your suggestion.

> > For eSDHC, after suspending, the power of esdhc controller will
> shutdown, we need to save the value of some registers before suspending,
> wich will used to restore the context after resuming.
> > For eSDHC, the bit DCR[DMA__AHB2MAG_IRQ_BYPASS] can't be set
> automatically, so we need to set it manually
> 
> If this is true for all revisions (be careful about the imx users), you
> don't
> need properties, but could simply set it.
I don't know the future SOC how to handle them, so I think it is safe to have the property