From: Arnd Bergmann <arnd@arndb.de>
To: dinguyen@altera.com
Cc: dinh.linux@gmail.com, cjb@laptop.org, jh80.chung@samsung.com,
tgih.jun@samsung.com, heiko@sntech.de, dianders@chromium.org,
alim.akhtar@samsung.com, bzhao@marvell.com,
linux-mmc@vger.kernel.org
Subject: Re: [PATCHv3 0/3] mmc: dw_mmc: Make the use of the hold reg generic
Date: Mon, 9 Dec 2013 17:12:19 +0100 [thread overview]
Message-ID: <201312091712.19872.arnd@arndb.de> (raw)
In-Reply-To: <1386564668-24738-1-git-send-email-dinguyen@altera.com>
On Monday 09 December 2013, dinguyen@altera.com wrote:
> This is v3 of the patch series that makes the setting of the SDMMC_CMD_USE_HOLD_REG
> bit generic.
>
> v3 differences:
>
> * Read the IHR(Implement HOLD Register) bit in the HCON register. Will not use
> the SDMMC_CMD_USE_HOLD_REG if the IHR bit is 0 and cclk_in_drv = 0.
>
> * Changes the cclk_in_drv and use_hold_reg register type from bool to u32.
>
> * Add can_use_hold_reg variable that is condition on whether or not we can use
> the hold reg.
>
> * v2 of (1/3, 2/3) was Acked-by: and Tested-by: Heiko Stuebner <heiko@sntech.de>
>
Acked-by: Arnd Bergmann <arnd@arndb.de>
prev parent reply other threads:[~2013-12-09 16:12 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-09 4:51 [PATCHv3 0/3] mmc: dw_mmc: Make the use of the hold reg generic dinguyen
2013-12-09 4:51 ` [PATCHv3 1/3] mmc: dw_mmc: Enable the hold reg for certain speed modes dinguyen
2013-12-09 9:56 ` Heiko Stübner
2013-12-09 16:15 ` Dinh Nguyen
2013-12-16 4:23 ` Seungwon Jeon
2013-12-16 4:44 ` Dinh Nguyen
2013-12-16 7:20 ` Seungwon Jeon
2013-12-16 16:38 ` Dinh Nguyen
2013-12-09 4:51 ` [PATCHv3 2/3] mmc: dw_mmc-pltm: Remove Rockchip's custom dw_mmc driver structure dinguyen
2013-12-09 4:51 ` [PATCHv3 3/3] mmc: dw_mmc-exynos: Remove Exynos' custom prepare_command function dinguyen
2013-12-09 16:12 ` Arnd Bergmann [this message]
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