From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH 2/3] mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers Date: Fri, 29 Jul 2016 21:36:34 +0200 Message-ID: <20160729193634.GA27116@lukather> References: <20160721085615.GG5993@lukather> <20160721112655.941b1dad04f7a5b94d4172c1@free.fr> Reply-To: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="WIyZ46R2i8wDzkSu" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Content-Disposition: inline In-Reply-To: <20160721112655.941b1dad04f7a5b94d4172c1-GANU6spQydw@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Jean-Francois Moine Cc: Ulf Hansson , Chen-Yu Tsai , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org List-Id: linux-mmc@vger.kernel.org --WIyZ46R2i8wDzkSu Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline On Thu, Jul 21, 2016 at 11:26:55AM +0200, Jean-Francois Moine wrote: > On Thu, 21 Jul 2016 10:56:15 +0200 > Maxime Ripard wrote: > > > On Wed, Jul 20, 2016 at 08:16:28PM +0200, Jean-Francois Moine wrote: > > > The 'new timing mode' with 8 bits DDR works correctly when the NewTiming > > > register is set. > > > > What does that mode brings to the table? > > From my tests, the eMMC of the Banana Pi M3 (A83T) cannot work when the > new mode is not used. That's odd. The one in the Pine64 seems to work just fine, and yet there's only the new mode on the A64. Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com --WIyZ46R2i8wDzkSu--