[PATCH/RFC 0/5 repost] mmc: renesas_sdhi: add support for R-Car Gen3 SDHI DMAC

[PATCH/RFC 0/5 repost] mmc: renesas_sdhi: add support for R-Car Gen3 SDHI DMAC

[Simon Horman]

Hi,

this series adds support for the internal DMAC used by r8a779[56] SoCs.
This is achieved by adding a new variant of the SDHI driver for this
DMA controller with compat strings for the r8a779[56] SoCs.
Compat strings for these SoCs are also removed from the existing SYS DMAC
variant of the SDHI driver.

Based on mmc/next

Headline performance boost: 9.5MB/s -> 39.7MB/s
More run-time information below.

Simon Horman (4):
  mmc: sh_mobile_sdhi: set max_segs and max_blk_count values R-Car Gen3
  mmc: tmio: add complete to DMA ops
  mmc: renesas_sdhi: add support for R-Car Gen3 SDHI DMAC
  mmc: renesas-sdhi: remove gen3 support from sysc dmac driver

Yoshihiro Shimoda (1):
  mmc: tmio: add max_segs and max_blk_count in tmio_mmc_data

 drivers/mmc/host/Kconfig                      |  17 ++
 drivers/mmc/host/Makefile                     |   8 +-
 drivers/mmc/host/renesas_sdhi.h               |   2 +
 drivers/mmc/host/renesas_sdhi_core.c          |   2 +
 drivers/mmc/host/renesas_sdhi_internal_dmac.c | 275 ++++++++++++++++++++++++++
 drivers/mmc/host/renesas_sdhi_sys_dmac.c      |  23 +--
 drivers/mmc/host/tmio_mmc.h                   |   2 +
 drivers/mmc/host/tmio_mmc_core.c              |  16 +-
 include/linux/mfd/tmio.h                      |   2 +
 9 files changed, 319 insertions(+), 28 deletions(-)
 create mode 100644 drivers/mmc/host/renesas_sdhi_internal_dmac.c

-- 
2.1.4

M3-W ES1.0

fd9437fc8884 (topic/sdhi-gen3-dma-2017) mmc: renesas-sdhi: remove gen3 support from sysc dmac driver

# dmesg | egrep '(sd|mmc)'
[    1.412911] sdhci: Secure Digital Host Controller Interface driver
[    1.419120] sdhci: Copyright(c) Pierre Ossman
[    1.423990] renesas_sdhi_internal_dmac ee100000.sd: Got CD GPIO
[    1.429951] renesas_sdhi_internal_dmac ee100000.sd: Got WP GPIO
[    1.560503] renesas_sdhi_internal_dmac ee140000.sd: mmc0 base at 0xee140000 max clock rate 200 MHz
[    1.569871] renesas_sdhi_internal_dmac ee160000.sd: Got CD GPIO
[    1.575846] renesas_sdhi_internal_dmac ee160000.sd: Got WP GPIO
[    1.590584] sdhci-pltfm: SDHCI platform and OF driver helper
[    1.638687] renesas_sdhi_internal_dmac ee100000.sd: Got CD GPIO
[    1.644661] renesas_sdhi_internal_dmac ee100000.sd: Got WP GPIO
[    1.772556] renesas_sdhi_internal_dmac ee100000.sd: mmc1 base at 0xee100000 max clock rate 200 MHz
[    1.782613] renesas_sdhi_internal_dmac ee160000.sd: Got CD GPIO
[    1.788580] renesas_sdhi_internal_dmac ee160000.sd: Got WP GPIO
[    1.842940] mmc0: new high speed MMC card at address 0001
[    1.852857] mmcblk0: mmc0:0001 eMMC   28.8 GiB
[    1.857624] mmcblk0boot0: mmc0:0001 eMMC   partition 1 4.00 MiB
[    1.867734] mmcblk0boot1: mmc0:0001 eMMC   partition 2 4.00 MiB
[    1.877858] mmcblk0rpmb: mmc0:0001 eMMC   partition 3 4.00 MiB
[    1.887028]  mmcblk0: p1
[    1.916589] renesas_sdhi_internal_dmac ee160000.sd: mmc2 base at 0xee160000 max clock rate 200 MHz
[    2.060534] mmc1: new ultra high speed SDR50 SDHC card at address e624
[    2.071600] mmcblk1: mmc1:e624 SU08G 7.40 GiB
[    2.086875]  mmcblk1: p1
[    2.260532] mmc2: new ultra high speed SDR50 SDHC card at address 0001
[    2.267407] mmcblk2: mmc2:0001 00000 29.8 GiB
[    2.281572]  mmcblk2: p1

# grep sd /proc/interrupts
100:      24972          0     GIC-0 197 Level     ee100000.sd
101:        604          0     GIC-0 199 Level     ee140000.sd
102:      24980          0     GIC-0 200 Level     ee160000.sd
178:          0          0  e6053000.gpio  12 Edge      ee100000.sd cd
197:          0          0  e6054000.gpio  15 Edge      ee160000.sd cd

# cat /sys/devices/platform/soc/ee100000.sd/mmc_host/mmc1/mmc1:e624
035344535530384780b1b8a11200d300
# dd if=/dev/mmcblk1 of=/dev/null bs=1M count=512 iflag=direct
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 13.5376 s, 39.7 MB/s

# cat /sys/devices/platform/soc/ee160000.sd/mmc_host/mmc2/mmc2:0001
1b534d3030303030103916141700f600
# dd if=/dev/mmcblk2 of=/dev/null bs=1M count=512 iflag=direct
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 17.5562 s, 30.6 MB/s

# grep sd /proc/interrupts
100:      49548          0     GIC-0 197 Level     ee100000.sd
101:        604          0     GIC-0 199 Level     ee140000.sd
102:      49556          0     GIC-0 200 Level     ee160000.sd
178:          0          0  e6053000.gpio  12 Edge      ee100000.sd cd
197:          0          0  e6054000.gpio  15 Edge      ee160000.sd cd

-----------------------

6e75316c15df (mmc/next) mmc: tmio: make sure SDIO gets reinitialized after resume

# dmesg | egrep '(sd|mmc)'
[    1.428112] sdhci: Secure Digital Host Controller Interface driver
[    1.434620] sdhci: Copyright(c) Pierre Ossman
[    1.439831] sh_mobile_sdhi ee100000.sd: Got CD GPIO
[    1.444764] sh_mobile_sdhi ee100000.sd: Got WP GPIO
[    1.571160] sh_mobile_sdhi ee140000.sd: mmc0 base at 0xee140000 max clock rate 200 MHz
[    1.579496] sh_mobile_sdhi ee160000.sd: Got CD GPIO
[    1.584434] sh_mobile_sdhi ee160000.sd: Got WP GPIO
[    1.598138] sdhci-pltfm: SDHCI platform and OF driver helper
[    1.647916] sh_mobile_sdhi ee100000.sd: Got CD GPIO
[    1.652857] sh_mobile_sdhi ee100000.sd: Got WP GPIO
[    1.779234] sh_mobile_sdhi ee100000.sd: mmc1 base at 0xee100000 max clock rate 200 MHz
[    1.788368] sh_mobile_sdhi ee160000.sd: Got CD GPIO
[    1.793300] sh_mobile_sdhi ee160000.sd: Got WP GPIO
[    1.832493] mmc0: new high speed MMC card at address 0001
[    1.842368] mmcblk0: mmc0:0001 eMMC   28.8 GiB
[    1.851133] mmcblk0boot0: mmc0:0001 eMMC   partition 1 4.00 MiB
[    1.857245] mmcblk0boot1: mmc0:0001 eMMC   partition 2 4.00 MiB
[    1.867323] mmcblk0rpmb: mmc0:0001 eMMC   partition 3 4.00 MiB
[    1.876809]  mmcblk0: p1
[    1.919252] sh_mobile_sdhi ee160000.sd: mmc2 base at 0xee160000 max clock rate 200 MHz
[    2.063208] mmc1: new ultra high speed SDR50 SDHC card at address e624
[    2.074300] mmcblk1: mmc1:e624 SU08G 7.40 GiB
[    2.089887]  mmcblk1: p1
[    2.263192] mmc2: new ultra high speed SDR50 SDHC card at address 0001
[    2.270073] mmcblk2: mmc2:0001 00000 29.8 GiB
[    2.284583]  mmcblk2: p1

# grep sd /proc/interrupts
100:       2276          0     GIC-0 197 Level     ee100000.sd
101:       3040          0     GIC-0 199 Level     ee140000.sd
102:       2284          0     GIC-0 200 Level     ee160000.sd
178:          0          0  e6053000.gpio  12 Edge      ee100000.sd cd
197:          0          0  e6054000.gpio  15 Edge      ee160000.sd cd

# cat /sys/devices/platform/soc/ee100000.sd/mmc_host/mmc1/mmc1:e624 
035344535530384780b1b8a11200d300

# cat /sys/devices/platform/soc/ee160000.sd/mmc_host/mmc2/mmc2:0001 
1b534d3030303030103916141700f600
# dd if=/dev/mmcblk2 of=/dev/null bs=1M count=512 iflag=direct
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 56.7809 s, 9.5 MB/s

# grep sd /proc/interrupts
100:       2276          0     GIC-0 197 Level     ee100000.sd
101:       3040          0     GIC-0 199 Level     ee140000.sd
102:    2124012          0     GIC-0 200 Level     ee160000.sd
178:          0          0  e6053000.gpio  12 Edge      ee100000.sd cd
197:          0          0  e6054000.gpio  15 Edge      ee160000.sd cd

[PATCH/RFC 1/5] mmc: tmio: add max_segs and max_blk_count in tmio_mmc_data

[Simon Horman]

From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

To change each value from related driver (e.g. sh_mobile_sdhi driver),
this patch adds these member in the struct tmio_mmc_data.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Ai Kyuse <ai.kyuse.uw@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/mmc/host/tmio_mmc_core.c | 6 +++---
 include/linux/mfd/tmio.h         | 2 ++
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
index ed4068125349..0e76e099dc7f 100644
--- a/drivers/mmc/host/tmio_mmc_core.c
+++ b/drivers/mmc/host/tmio_mmc_core.c
@@ -1247,10 +1247,10 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host,
 
 	mmc->caps |= MMC_CAP_4_BIT_DATA | pdata->capabilities;
 	mmc->caps2 |= pdata->capabilities2;
-	mmc->max_segs = 32;
+	mmc->max_segs = pdata->max_segs ? : 32;
 	mmc->max_blk_size = 512;
-	mmc->max_blk_count = (PAGE_SIZE / mmc->max_blk_size) *
-		mmc->max_segs;
+	mmc->max_blk_count = pdata->max_blk_count ? :
+		(PAGE_SIZE / mmc->max_blk_size) * mmc->max_segs;
 	mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
 	mmc->max_seg_size = mmc->max_req_size;
 
diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h
index c83c16b931a8..4e261ea94d6a 100644
--- a/include/linux/mfd/tmio.h
+++ b/include/linux/mfd/tmio.h
@@ -128,6 +128,8 @@ struct tmio_mmc_data {
 	unsigned int			cd_gpio;
 	int				alignment_shift;
 	dma_addr_t			dma_rx_offset;
+	unsigned int			max_blk_count;
+	unsigned short			max_segs;
 	void (*set_pwr)(struct platform_device *host, int state);
 	void (*set_clk_div)(struct platform_device *host, int state);
 };
-- 
2.1.4

[PATCH/RFC 2/5] mmc: sh_mobile_sdhi: set max_segs and max_blk_count values R-Car Gen3

[Simon Horman]

To avoid complicate code in own dma code for gen3, this patch
adds set max_segs to 1. Then, the tmio driver will get requests
as sg_len = 1 only.

In the performance point of view, the CONFIG_MMC_BLOCK_BOUNCE should
be set. Otherwise, mmc block layer will set 4-kbyte each as a request.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Ai Kyuse <ai.kyuse.uw@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/mmc/host/renesas_sdhi.h      | 2 ++
 drivers/mmc/host/renesas_sdhi_core.c | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdhi.h
index eb3ea15ff92d..6f7233fe32a2 100644
--- a/drivers/mmc/host/renesas_sdhi.h
+++ b/drivers/mmc/host/renesas_sdhi.h
@@ -31,6 +31,8 @@ struct renesas_sdhi_of_data {
 	int scc_offset;
 	struct renesas_sdhi_scc *taps;
 	int taps_num;
+	unsigned int max_blk_count;
+	unsigned short max_segs;
 };
 
 int renesas_sdhi_probe(struct platform_device *pdev,
diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
index 82150a966391..294bc9705c5f 100644
--- a/drivers/mmc/host/renesas_sdhi_core.c
+++ b/drivers/mmc/host/renesas_sdhi_core.c
@@ -522,6 +522,8 @@ int renesas_sdhi_probe(struct platform_device *pdev,
 		mmc_data->capabilities |= of_data->capabilities;
 		mmc_data->capabilities2 |= of_data->capabilities2;
 		mmc_data->dma_rx_offset = of_data->dma_rx_offset;
+		mmc_data->max_blk_count = of_data->max_blk_count;
+		mmc_data->max_segs = of_data->max_segs;
 		dma_priv->dma_buswidth = of_data->dma_buswidth;
 		host->bus_shift = of_data->bus_shift;
 	}
-- 
2.1.4

[PATCH/RFC 3/5] mmc: tmio: add complete to DMA ops

[Simon Horman]

Add complete to DMA ops to allow DMAC implementation dependent
handling of DMA completion.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/mmc/host/tmio_mmc.h      |  1 +
 drivers/mmc/host/tmio_mmc_core.c | 10 ++++++++--
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h
index 9c94b6eb9b49..82725f9de359 100644
--- a/drivers/mmc/host/tmio_mmc.h
+++ b/drivers/mmc/host/tmio_mmc.h
@@ -121,6 +121,7 @@ struct tmio_mmc_dma_ops {
 			struct tmio_mmc_data *pdata);
 	void (*release)(struct tmio_mmc_host *host);
 	void (*abort)(struct tmio_mmc_host *host);
+	void (*complete)(struct tmio_mmc_host *host);
 };
 
 struct tmio_mmc_host {
diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
index 0e76e099dc7f..26fe9bb64849 100644
--- a/drivers/mmc/host/tmio_mmc_core.c
+++ b/drivers/mmc/host/tmio_mmc_core.c
@@ -86,6 +86,12 @@ static inline void tmio_mmc_abort_dma(struct tmio_mmc_host *host)
 		host->dma_ops->abort(host);
 }
 
+static inline void tmio_mmc_complete_dma(struct tmio_mmc_host *host)
+{
+	if (host->dma_ops)
+		host->dma_ops->complete(host);
+}
+
 void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
 {
 	host->sdcard_irq_mask &= ~(i & TMIO_MASK_IRQ);
@@ -604,11 +610,11 @@ static void tmio_mmc_data_irq(struct tmio_mmc_host *host, unsigned int stat)
 
 		if (done) {
 			tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
-			complete(&host->dma_dataend);
+			tmio_mmc_complete_dma(host);
 		}
 	} else if (host->chan_rx && (data->flags & MMC_DATA_READ) && !host->force_pio) {
 		tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
-		complete(&host->dma_dataend);
+		tmio_mmc_complete_dma(host);
 	} else {
 		tmio_mmc_do_data_irq(host);
 		tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_READOP | TMIO_MASK_WRITEOP);
-- 
2.1.4

[PATCH/RFC 4/5] mmc: renesas_sdhi: add support for R-Car Gen3 SDHI DMAC

[Simon Horman]

R-Car Gen3 has a dedicated DMA controller for SDHI module. Since
the DMAC is in a part of SDHI module and is not suitable as dmaengine,
this patch adds a different code as tmio_mmc_dma_gen3.c.

Clearing of DM_CM_INFO1 after DMA thanks to Dirk Behme

Cc: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Ai Kyuse <ai.kyuse.uw@renesas.com>
---
 drivers/mmc/host/Kconfig                      |  17 ++
 drivers/mmc/host/Makefile                     |   8 +-
 drivers/mmc/host/renesas_sdhi_internal_dmac.c | 275 ++++++++++++++++++++++++++
 drivers/mmc/host/renesas_sdhi_sys_dmac.c      |   2 +-
 drivers/mmc/host/tmio_mmc.h                   |   1 +
 5 files changed, 301 insertions(+), 2 deletions(-)
 create mode 100644 drivers/mmc/host/renesas_sdhi_internal_dmac.c

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 5755b69f2f72..e813d420d7b3 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -575,10 +575,27 @@ config MMC_SDHI
 	depends on SUPERH || ARM || ARM64
 	depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
 	select MMC_TMIO_CORE
+	select MMC_SDHI_SYS_DMAC if (SUPERH || ARM)
+	select MMC_SDHI_INTERNAL_DMAC if ARM64
 	help
 	  This provides support for the SDHI SD/SDIO controller found in
 	  Renesas SuperH, ARM and ARM64 based SoCs
 
+config MMC_SDHI_SYS_DMAC
+	tristate "DMA support use of SYS DMAC with SDHI SD/SDIO controller"
+	depends on MMC_SDHI
+	help
+	  This provides DMA support for the SDHI SD/SDIO controller
+	  found in SuperH and Renesas ARM based SoCs.
+
+config MMC_SDHI_INTERNAL_DMAC
+	tristate "DMA support for Internal DMAC with SDHI SD/SDIO controller"
+	depends on ARM64 || COMPILE_TEST
+	depends on MMC_SDHI
+	help
+	  This provides DMA support for the SDHI SD/SDIO controller
+	  found in Renesas arm64 based SoCs.
+
 config MMC_CB710
 	tristate "ENE CB710 MMC/SD Interface support"
 	depends on PCI
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 4d4547116311..8c46766c000c 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -36,7 +36,13 @@ obj-$(CONFIG_MMC_S3C)   	+= s3cmci.o
 obj-$(CONFIG_MMC_SDRICOH_CS)	+= sdricoh_cs.o
 obj-$(CONFIG_MMC_TMIO)		+= tmio_mmc.o
 obj-$(CONFIG_MMC_TMIO_CORE)	+= tmio_mmc_core.o
-obj-$(CONFIG_MMC_SDHI)		+= renesas_sdhi_core.o renesas_sdhi_sys_dmac.o
+obj-$(CONFIG_MMC_SDHI)		+= renesas_sdhi_core.o
+ifeq ($(subst m,y,$(CONFIG_MMC_SDHI_SYS_DMAC)),y)
+obj-$(CONFIG_MMC_SDHI)		+= renesas_sdhi_sys_dmac.o
+endif
+ifeq ($(subst m,y,$(CONFIG_MMC_SDHI_INTERNAL_DMAC)),y)
+obj-$(CONFIG_MMC_SDHI)		+= renesas_sdhi_internal_dmac.o
+endif
 obj-$(CONFIG_MMC_CB710)		+= cb710-mmc.o
 obj-$(CONFIG_MMC_VIA_SDMMC)	+= via-sdmmc.o
 obj-$(CONFIG_SDH_BFIN)		+= bfin_sdh.o
diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
new file mode 100644
index 000000000000..a16b616a2c96
--- /dev/null
+++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
@@ -0,0 +1,275 @@
+/*
+ * DMA support for Internal DMAC with SDHI SD/SDIO controller
+ *
+ * Copyright (C) 2016-17 Renesas Electronics Corporation
+ * Copyright (C) 2016-17 Horms Solutions, Simon Horman
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/mfd/tmio.h>
+#include <linux/mmc/host.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/pagemap.h>
+#include <linux/scatterlist.h>
+
+#include "renesas_sdhi.h"
+#include "tmio_mmc.h"
+
+#define DM_CM_DTRAN_MODE	0x820
+#define DM_CM_DTRAN_CTRL	0x828
+#define DM_CM_RST		0x830
+#define DM_CM_INFO1		0x840
+#define DM_CM_INFO1_MASK	0x848
+#define DM_CM_INFO2		0x850
+#define DM_CM_INFO2_MASK	0x858
+#define DM_DTRAN_ADDR		0x880
+
+/* DM_CM_DTRAN_MODE */
+#define DTRAN_MODE_CH_NUM_CH0	0	/* "downstream" = for write commands */
+#define DTRAN_MODE_CH_NUM_CH1	BIT(16)	/* "uptream" = for read commands */
+#define DTRAN_MODE_BUS_WID_TH	(BIT(5) | BIT(4))
+#define DTRAN_MODE_ADDR_MODE	BIT(0)	/* 1 = Increment address */
+
+/* DM_CM_DTRAN_CTRL */
+#define DTRAN_CTRL_DM_START	BIT(0)
+
+/* DM_CM_RST */
+#define RST_DTRANRST1		BIT(9)
+#define RST_DTRANRST0		BIT(8)
+#define RST_RESERVED_BITS	GENMASK_ULL(32, 0)
+
+/* DM_CM_INFO1 and DM_CM_INFO1_MASK */
+#define INFO1_CLEAR		0
+#define INFO1_DTRANEND1		BIT(17)
+#define INFO1_DTRANEND0		BIT(16)
+
+/* DM_CM_INFO2 and DM_CM_INFO2_MASK */
+#define INFO2_DTRANERR1		BIT(17)
+#define INFO2_DTRANERR0		BIT(16)
+
+/*
+ * Specification of this driver:
+ * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma
+ * - Since this SDHI DMAC register set has actual 32-bit and "bus_shift" is 2,
+ *   this driver cannot use original sd_ctrl_{write,read}32 functions.
+ */
+
+/* Definitions for sampling clocks */
+static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
+	{
+		.clk_rate = 0,
+		.tap = 0x00000300,
+	},
+};
+
+static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
+	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE |
+			  TMIO_MMC_CLK_ACTUAL | TMIO_MMC_MIN_RCAR2,
+	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+			  MMC_CAP_CMD23,
+	.bus_shift	= 2,
+	.scc_offset	= 0x1000,
+	.taps		= rcar_gen3_scc_taps,
+	.taps_num	= ARRAY_SIZE(rcar_gen3_scc_taps),
+	/* Gen3 SDHI DMAC can handle 0xffffffff blk count, but seg = 1 */
+	.max_blk_count	= 0xffffffff,
+	.max_segs	= 1,
+};
+
+static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
+	{ .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
+	{ .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
+	{},
+};
+MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match);
+
+static void
+renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host,
+				    int addr, u64 val)
+{
+	writeq(val, host->ctl + addr);
+}
+
+static void
+renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable)
+{
+	if (!host->chan_tx || !host->chan_rx)
+		return;
+
+	if (!enable)
+		renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1,
+						    INFO1_CLEAR);
+
+	if (host->dma->enable)
+		host->dma->enable(host, enable);
+}
+
+static void
+renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) {
+	u64 val = RST_DTRANRST1 | RST_DTRANRST0;
+
+	renesas_sdhi_internal_dmac_enable_dma(host, false);
+
+	renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
+					    RST_RESERVED_BITS & ~val);
+	renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
+					    RST_RESERVED_BITS | val);
+
+	renesas_sdhi_internal_dmac_enable_dma(host, true);
+}
+
+static void
+renesas_sdhi_internal_dmac_complete_dma(struct tmio_mmc_host *host) {
+	tasklet_schedule(&host->dma_complete);
+}
+
+static void
+renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
+				     struct mmc_data *data)
+{
+	struct scatterlist *sg = host->sg_ptr;
+	u32 dtran_mode = DTRAN_MODE_BUS_WID_TH | DTRAN_MODE_ADDR_MODE;
+	enum dma_data_direction dir;
+	int ret;
+	u32 irq_mask;
+
+	/* This DMAC cannot handle if sg_len is not 1 */
+	WARN_ON(host->sg_len > 1);
+
+	/* This DMAC cannot handle if buffer is not 8-bytes alignment */
+	if (!IS_ALIGNED(sg->offset, 8)) {
+		host->force_pio = true;
+		renesas_sdhi_internal_dmac_enable_dma(host, false);
+		return;
+	}
+
+	if (data->flags & MMC_DATA_READ) {
+		dtran_mode |= DTRAN_MODE_CH_NUM_CH1;
+		dir = DMA_FROM_DEVICE;
+		irq_mask = TMIO_STAT_RXRDY;
+	} else {
+		dtran_mode |= DTRAN_MODE_CH_NUM_CH0;
+		dir = DMA_TO_DEVICE;
+		irq_mask = TMIO_STAT_TXRQ;
+	}
+
+	ret = dma_map_sg(&host->pdev->dev, sg, host->sg_len, dir);
+	if (ret < 0) {
+		dev_err(&host->pdev->dev, "%s: dma_map_sg failed\n", __func__);
+		return;
+	}
+
+	renesas_sdhi_internal_dmac_enable_dma(host, true);
+
+	/* disable PIO irqs to avoid "PIO IRQ in DMA mode!" */
+	tmio_mmc_disable_mmc_irqs(host, irq_mask);
+
+	/* set dma parameters */
+	renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE,
+					    dtran_mode);
+	renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR,
+					    sg->dma_address);
+}
+
+static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg)
+{
+	struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
+
+	tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
+
+	/* start the DMAC */
+	renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL,
+					    DTRAN_CTRL_DM_START);
+}
+
+static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg)
+{
+	struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
+	enum dma_data_direction dir;
+
+	spin_lock_irq(&host->lock);
+
+	if (!host->data)
+		goto out;
+
+	if (host->data->flags & MMC_DATA_READ)
+		dir = DMA_FROM_DEVICE;
+	else
+		dir = DMA_TO_DEVICE;
+
+	renesas_sdhi_internal_dmac_enable_dma(host, false);
+	dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->sg_len, dir);
+
+	spin_unlock_irq(&host->lock);
+
+	spin_lock_irq(&host->lock);
+	tmio_mmc_do_data_irq(host);
+out:
+	spin_unlock_irq(&host->lock);
+}
+
+static void
+renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host,
+				       struct tmio_mmc_data *pdata)
+{
+	/* Each value is set to non-zero to assume "enabling" each DMA */
+	host->chan_rx = host->chan_tx = (void *)0xdeadbeaf;
+
+	tasklet_init(&host->dma_complete,
+		     renesas_sdhi_internal_dmac_complete_tasklet_fn,
+		     (unsigned long)host);
+	tasklet_init(&host->dma_issue,
+		     renesas_sdhi_internal_dmac_issue_tasklet_fn,
+		     (unsigned long)host);
+}
+
+static void
+renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host)
+{
+	/* Each value is set to zero to assume "disabling" each DMA */
+	host->chan_rx = host->chan_tx = NULL;
+}
+
+static struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = {
+	.start = renesas_sdhi_internal_dmac_start_dma,
+	.enable = renesas_sdhi_internal_dmac_enable_dma,
+	.request = renesas_sdhi_internal_dmac_request_dma,
+	.release = renesas_sdhi_internal_dmac_release_dma,
+	.abort = renesas_sdhi_internal_dmac_abort_dma,
+	.complete = renesas_sdhi_internal_dmac_complete_dma,
+};
+
+static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev)
+{
+	return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops);
+}
+
+static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+				pm_runtime_force_resume)
+	SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
+			   tmio_mmc_host_runtime_resume,
+			   NULL)
+};
+
+static struct platform_driver renesas_internal_dmac_sdhi_driver = {
+	.driver		= {
+		.name	= "renesas_sdhi_internal_dmac",
+		.pm	= &renesas_sdhi_internal_dmac_dev_pm_ops,
+		.of_match_table = renesas_sdhi_internal_dmac_of_match,
+	},
+	.probe		= renesas_sdhi_internal_dmac_probe,
+	.remove		= renesas_sdhi_remove,
+};
+
+module_platform_driver(renesas_internal_dmac_sdhi_driver);
+
+MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC");
+MODULE_AUTHOR("Yoshihiro Shimoda");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
index 7eab55adc5b2..cc3e0f94b276 100644
--- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
@@ -1,5 +1,5 @@
 /*
- * DMA function for TMIO MMC implementations
+ * DMA support use of SYS DMAC with SDHI SD/SDIO controller
  *
  * Copyright (C) 2010-2011 Guennadi Liakhovetski
  *
diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h
index 82725f9de359..3b08c76a55e7 100644
--- a/drivers/mmc/host/tmio_mmc.h
+++ b/drivers/mmc/host/tmio_mmc.h
@@ -151,6 +151,7 @@ struct tmio_mmc_host {
 	struct dma_chan		*chan_rx;
 	struct dma_chan		*chan_tx;
 	struct completion	dma_dataend;
+	struct tasklet_struct	dma_complete;
 	struct tasklet_struct	dma_issue;
 	struct scatterlist	bounce_sg;
 	u8			*bounce_buf;
-- 
2.1.4

Re: [PATCH/RFC 4/5] mmc: renesas_sdhi: add support for R-Car Gen3 SDHI DMAC

[Geert Uytterhoeven]

Hi Simon,

On Thu, Jun 8, 2017 at 3:13 PM, Simon Horman <horms+renesas@verge.net.au> wrote:
> R-Car Gen3 has a dedicated DMA controller for SDHI module. Since
> the DMAC is in a part of SDHI module and is not suitable as dmaengine,

the DMAC is part of the SDHI module?

> this patch adds a different code as tmio_mmc_dma_gen3.c.

adds different code?

> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -575,10 +575,27 @@ config MMC_SDHI
>         depends on SUPERH || ARM || ARM64
>         depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
>         select MMC_TMIO_CORE
> +       select MMC_SDHI_SYS_DMAC if (SUPERH || ARM)
> +       select MMC_SDHI_INTERNAL_DMAC if ARM64
>         help
>           This provides support for the SDHI SD/SDIO controller found in
>           Renesas SuperH, ARM and ARM64 based SoCs
>
> +config MMC_SDHI_SYS_DMAC
> +       tristate "DMA support use of SYS DMAC with SDHI SD/SDIO controller"

DMA support for SYS_DMAC?


Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH/RFC 4/5] mmc: renesas_sdhi: add support for R-Car Gen3 SDHI DMAC

[Simon Horman]

On Fri, Jun 09, 2017 at 09:39:49AM +0200, Geert Uytterhoeven wrote:
> Hi Simon,
> 
> On Thu, Jun 8, 2017 at 3:13 PM, Simon Horman <horms+renesas@verge.net.au> wrote:
> > R-Car Gen3 has a dedicated DMA controller for SDHI module. Since
> > the DMAC is in a part of SDHI module and is not suitable as dmaengine,
> 
> the DMAC is part of the SDHI module?
> 
> > this patch adds a different code as tmio_mmc_dma_gen3.c.
> 
> adds different code?
> 
> > --- a/drivers/mmc/host/Kconfig
> > +++ b/drivers/mmc/host/Kconfig
> > @@ -575,10 +575,27 @@ config MMC_SDHI
> >         depends on SUPERH || ARM || ARM64
> >         depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
> >         select MMC_TMIO_CORE
> > +       select MMC_SDHI_SYS_DMAC if (SUPERH || ARM)
> > +       select MMC_SDHI_INTERNAL_DMAC if ARM64
> >         help
> >           This provides support for the SDHI SD/SDIO controller found in
> >           Renesas SuperH, ARM and ARM64 based SoCs
> >
> > +config MMC_SDHI_SYS_DMAC
> > +       tristate "DMA support use of SYS DMAC with SDHI SD/SDIO controller"
> 
> DMA support for SYS_DMAC?

How about this?

config MMC_SDHI_SYS_DMAC
	tristate "DMA for SDHI SD/SDIO controllers using SYS-DMAC"
	...
	help
	   This provides DMA support for the SDHI SD/SDIO controllers
	   using SYS-DMAC via DMA Engine. This supports the controllers
	   found in SuperH and Renesas ARM based SoCs.

config MMC_SDHI_INTERNAL_DMAC
	tristate "DMA for SDHI SD/SDIO controllers using on-chip bus mastering"
	...
	help
	   This provides DMA support for the SDHI SD/SDIO controllers
	   using on-chip bus mastering. This supports the controllers
	   found in arm64 based SoCs.

> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds
> 

Re: [PATCH/RFC 4/5] mmc: renesas_sdhi: add support for R-Car Gen3 SDHI DMAC

[Geert Uytterhoeven]

Hi Simon,

On Fri, Jun 16, 2017 at 9:12 AM, Simon Horman <horms@verge.net.au> wrote:
> On Fri, Jun 09, 2017 at 09:39:49AM +0200, Geert Uytterhoeven wrote:
>> On Thu, Jun 8, 2017 at 3:13 PM, Simon Horman <horms+renesas@verge.net.au> wrote:
>> > R-Car Gen3 has a dedicated DMA controller for SDHI module. Since
>> > the DMAC is in a part of SDHI module and is not suitable as dmaengine,

>> > --- a/drivers/mmc/host/Kconfig
>> > +++ b/drivers/mmc/host/Kconfig

>> > +config MMC_SDHI_SYS_DMAC
>> > +       tristate "DMA support use of SYS DMAC with SDHI SD/SDIO controller"
>>
>> DMA support for SYS_DMAC?
>
> How about this?
>
> config MMC_SDHI_SYS_DMAC
>         tristate "DMA for SDHI SD/SDIO controllers using SYS-DMAC"

Better!

>         ...
>         help
>            This provides DMA support for the SDHI SD/SDIO controllers
>            using SYS-DMAC via DMA Engine. This supports the controllers

I would drop "the".

>            found in SuperH and Renesas ARM based SoCs.
>
> config MMC_SDHI_INTERNAL_DMAC
>         tristate "DMA for SDHI SD/SDIO controllers using on-chip bus mastering"
>         ...
>         help
>            This provides DMA support for the SDHI SD/SDIO controllers
>            using on-chip bus mastering. This supports the controllers

Likewise.

>            found in arm64 based SoCs.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH/RFC 4/5] mmc: renesas_sdhi: add support for R-Car Gen3 SDHI DMAC

[Simon Horman]

On Fri, Jun 16, 2017 at 09:21:04AM +0200, Geert Uytterhoeven wrote:
> Hi Simon,
> 
> On Fri, Jun 16, 2017 at 9:12 AM, Simon Horman <horms@verge.net.au> wrote:
> > On Fri, Jun 09, 2017 at 09:39:49AM +0200, Geert Uytterhoeven wrote:
> >> On Thu, Jun 8, 2017 at 3:13 PM, Simon Horman <horms+renesas@verge.net.au> wrote:
> >> > R-Car Gen3 has a dedicated DMA controller for SDHI module. Since
> >> > the DMAC is in a part of SDHI module and is not suitable as dmaengine,
> 
> >> > --- a/drivers/mmc/host/Kconfig
> >> > +++ b/drivers/mmc/host/Kconfig
> 
> >> > +config MMC_SDHI_SYS_DMAC
> >> > +       tristate "DMA support use of SYS DMAC with SDHI SD/SDIO controller"
> >>
> >> DMA support for SYS_DMAC?
> >
> > How about this?
> >
> > config MMC_SDHI_SYS_DMAC
> >         tristate "DMA for SDHI SD/SDIO controllers using SYS-DMAC"
> 
> Better!
> 
> >         ...
> >         help
> >            This provides DMA support for the SDHI SD/SDIO controllers
> >            using SYS-DMAC via DMA Engine. This supports the controllers
> 
> I would drop "the".

Will do, thanks.

> >            found in SuperH and Renesas ARM based SoCs.
> >
> > config MMC_SDHI_INTERNAL_DMAC
> >         tristate "DMA for SDHI SD/SDIO controllers using on-chip bus mastering"
> >         ...
> >         help
> >            This provides DMA support for the SDHI SD/SDIO controllers
> >            using on-chip bus mastering. This supports the controllers
> 
> Likewise.
> 
> >            found in arm64 based SoCs.
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds
> 

[PATCH/RFC 5/5] mmc: renesas-sdhi: remove gen3 support from sysc dmac driver

[Simon Horman]

Gen3 SoCs are now supported by the internal dmac variant of the SDHI driver.
Remove them from the sys dmac variant where only PIO mode is supported.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/mmc/host/renesas_sdhi_sys_dmac.c | 21 ---------------------
 1 file changed, 21 deletions(-)

diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
index cc3e0f94b276..1f8863e725aa 100644
--- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
@@ -63,25 +63,6 @@ static const struct renesas_sdhi_of_data of_rcar_gen2_compatible = {
 	.taps_num	= ARRAY_SIZE(rcar_gen2_scc_taps),
 };
 
-/* Definitions for sampling clocks */
-static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
-	{
-		.clk_rate = 0,
-		.tap = 0x00000300,
-	},
-};
-
-static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
-	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE |
-			  TMIO_MMC_CLK_ACTUAL | TMIO_MMC_MIN_RCAR2,
-	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
-			  MMC_CAP_CMD23,
-	.bus_shift	= 2,
-	.scc_offset	= 0x1000,
-	.taps		= rcar_gen3_scc_taps,
-	.taps_num	= ARRAY_SIZE(rcar_gen3_scc_taps),
-};
-
 static const struct of_device_id renesas_sdhi_sys_dmac_of_match[] = {
 	{ .compatible = "renesas,sdhi-shmobile" },
 	{ .compatible = "renesas,sdhi-sh73a0", .data = &of_default_cfg, },
@@ -95,8 +76,6 @@ static const struct of_device_id renesas_sdhi_sys_dmac_of_match[] = {
 	{ .compatible = "renesas,sdhi-r8a7792", .data = &of_rcar_gen2_compatible, },
 	{ .compatible = "renesas,sdhi-r8a7793", .data = &of_rcar_gen2_compatible, },
 	{ .compatible = "renesas,sdhi-r8a7794", .data = &of_rcar_gen2_compatible, },
-	{ .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
-	{ .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
 	{},
 };
 MODULE_DEVICE_TABLE(of, renesas_sdhi_sys_dmac_of_match);
-- 
2.1.4

[PATCH/RFC 0/5] mmc: renesas_sdhi: add support for R-Car Gen3 SDHI DMAC

[Simon Horman]

Hi,

this series adds support for the internal DMAC used by r8a779[56] SoCs.
This is achieved by adding a new variant of the SDHI driver for this
DMA controller with compat strings for the r8a779[56] SoCs.
Compat strings for these SoCs are also removed from the existing SYS DMAC
variant of the SDHI driver.

Based on mmc/next

Headline performance boost: 9.5MB/s -> 39.7MB/s
More run-time information below.

Simon Horman (4):
  mmc: sh_mobile_sdhi: set max_segs and max_blk_count values R-Car Gen3
  mmc: tmio: add complete to DMA ops
  mmc: renesas_sdhi: add support for R-Car Gen3 SDHI DMAC
  mmc: renesas-sdhi: remove gen3 support from sysc dmac driver

Yoshihiro Shimoda (1):
  mmc: tmio: add max_segs and max_blk_count in tmio_mmc_data

 drivers/mmc/host/Kconfig                      |  17 ++
 drivers/mmc/host/Makefile                     |   8 +-
 drivers/mmc/host/renesas_sdhi.h               |   2 +
 drivers/mmc/host/renesas_sdhi_core.c          |   2 +
 drivers/mmc/host/renesas_sdhi_internal_dmac.c | 275 ++++++++++++++++++++++++++
 drivers/mmc/host/renesas_sdhi_sys_dmac.c      |  23 +--
 drivers/mmc/host/tmio_mmc.h                   |   2 +
 drivers/mmc/host/tmio_mmc_core.c              |  16 +-
 include/linux/mfd/tmio.h                      |   2 +
 9 files changed, 319 insertions(+), 28 deletions(-)
 create mode 100644 drivers/mmc/host/renesas_sdhi_internal_dmac.c

-- 
2.1.4

M3-W ES1.0

fd9437fc8884 (topic/sdhi-gen3-dma-2017) mmc: renesas-sdhi: remove gen3 support from sysc dmac driver

# dmesg | egrep '(sd|mmc)'
[    1.412911] sdhci: Secure Digital Host Controller Interface driver
[    1.419120] sdhci: Copyright(c) Pierre Ossman
[    1.423990] renesas_sdhi_internal_dmac ee100000.sd: Got CD GPIO
[    1.429951] renesas_sdhi_internal_dmac ee100000.sd: Got WP GPIO
[    1.560503] renesas_sdhi_internal_dmac ee140000.sd: mmc0 base at 0xee140000 max clock rate 200 MHz
[    1.569871] renesas_sdhi_internal_dmac ee160000.sd: Got CD GPIO
[    1.575846] renesas_sdhi_internal_dmac ee160000.sd: Got WP GPIO
[    1.590584] sdhci-pltfm: SDHCI platform and OF driver helper
[    1.638687] renesas_sdhi_internal_dmac ee100000.sd: Got CD GPIO
[    1.644661] renesas_sdhi_internal_dmac ee100000.sd: Got WP GPIO
[    1.772556] renesas_sdhi_internal_dmac ee100000.sd: mmc1 base at 0xee100000 max clock rate 200 MHz
[    1.782613] renesas_sdhi_internal_dmac ee160000.sd: Got CD GPIO
[    1.788580] renesas_sdhi_internal_dmac ee160000.sd: Got WP GPIO
[    1.842940] mmc0: new high speed MMC card at address 0001
[    1.852857] mmcblk0: mmc0:0001 eMMC   28.8 GiB
[    1.857624] mmcblk0boot0: mmc0:0001 eMMC   partition 1 4.00 MiB
[    1.867734] mmcblk0boot1: mmc0:0001 eMMC   partition 2 4.00 MiB
[    1.877858] mmcblk0rpmb: mmc0:0001 eMMC   partition 3 4.00 MiB
[    1.887028]  mmcblk0: p1
[    1.916589] renesas_sdhi_internal_dmac ee160000.sd: mmc2 base at 0xee160000 max clock rate 200 MHz
[    2.060534] mmc1: new ultra high speed SDR50 SDHC card at address e624
[    2.071600] mmcblk1: mmc1:e624 SU08G 7.40 GiB
[    2.086875]  mmcblk1: p1
[    2.260532] mmc2: new ultra high speed SDR50 SDHC card at address 0001
[    2.267407] mmcblk2: mmc2:0001 00000 29.8 GiB
[    2.281572]  mmcblk2: p1

# grep sd /proc/interrupts
100:      24972          0     GIC-0 197 Level     ee100000.sd
101:        604          0     GIC-0 199 Level     ee140000.sd
102:      24980          0     GIC-0 200 Level     ee160000.sd
178:          0          0  e6053000.gpio  12 Edge      ee100000.sd cd
197:          0          0  e6054000.gpio  15 Edge      ee160000.sd cd

# cat /sys/devices/platform/soc/ee100000.sd/mmc_host/mmc1/mmc1:e624
035344535530384780b1b8a11200d300
# dd if=/dev/mmcblk1 of=/dev/null bs=1M count=512 iflag=direct
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 13.5376 s, 39.7 MB/s

# cat /sys/devices/platform/soc/ee160000.sd/mmc_host/mmc2/mmc2:0001
1b534d3030303030103916141700f600
# dd if=/dev/mmcblk2 of=/dev/null bs=1M count=512 iflag=direct
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 17.5562 s, 30.6 MB/s

# grep sd /proc/interrupts
100:      49548          0     GIC-0 197 Level     ee100000.sd
101:        604          0     GIC-0 199 Level     ee140000.sd
102:      49556          0     GIC-0 200 Level     ee160000.sd
178:          0          0  e6053000.gpio  12 Edge      ee100000.sd cd
197:          0          0  e6054000.gpio  15 Edge      ee160000.sd cd

-----------------------

6e75316c15df (mmc/next) mmc: tmio: make sure SDIO gets reinitialized after resume

# dmesg | egrep '(sd|mmc)'
[    1.428112] sdhci: Secure Digital Host Controller Interface driver
[    1.434620] sdhci: Copyright(c) Pierre Ossman
[    1.439831] sh_mobile_sdhi ee100000.sd: Got CD GPIO
[    1.444764] sh_mobile_sdhi ee100000.sd: Got WP GPIO
[    1.571160] sh_mobile_sdhi ee140000.sd: mmc0 base at 0xee140000 max clock rate 200 MHz
[    1.579496] sh_mobile_sdhi ee160000.sd: Got CD GPIO
[    1.584434] sh_mobile_sdhi ee160000.sd: Got WP GPIO
[    1.598138] sdhci-pltfm: SDHCI platform and OF driver helper
[    1.647916] sh_mobile_sdhi ee100000.sd: Got CD GPIO
[    1.652857] sh_mobile_sdhi ee100000.sd: Got WP GPIO
[    1.779234] sh_mobile_sdhi ee100000.sd: mmc1 base at 0xee100000 max clock rate 200 MHz
[    1.788368] sh_mobile_sdhi ee160000.sd: Got CD GPIO
[    1.793300] sh_mobile_sdhi ee160000.sd: Got WP GPIO
[    1.832493] mmc0: new high speed MMC card at address 0001
[    1.842368] mmcblk0: mmc0:0001 eMMC   28.8 GiB
[    1.851133] mmcblk0boot0: mmc0:0001 eMMC   partition 1 4.00 MiB
[    1.857245] mmcblk0boot1: mmc0:0001 eMMC   partition 2 4.00 MiB
[    1.867323] mmcblk0rpmb: mmc0:0001 eMMC   partition 3 4.00 MiB
[    1.876809]  mmcblk0: p1
[    1.919252] sh_mobile_sdhi ee160000.sd: mmc2 base at 0xee160000 max clock rate 200 MHz
[    2.063208] mmc1: new ultra high speed SDR50 SDHC card at address e624
[    2.074300] mmcblk1: mmc1:e624 SU08G 7.40 GiB
[    2.089887]  mmcblk1: p1
[    2.263192] mmc2: new ultra high speed SDR50 SDHC card at address 0001
[    2.270073] mmcblk2: mmc2:0001 00000 29.8 GiB
[    2.284583]  mmcblk2: p1

# grep sd /proc/interrupts
100:       2276          0     GIC-0 197 Level     ee100000.sd
101:       3040          0     GIC-0 199 Level     ee140000.sd
102:       2284          0     GIC-0 200 Level     ee160000.sd
178:          0          0  e6053000.gpio  12 Edge      ee100000.sd cd
197:          0          0  e6054000.gpio  15 Edge      ee160000.sd cd

# cat /sys/devices/platform/soc/ee100000.sd/mmc_host/mmc1/mmc1:e624 
035344535530384780b1b8a11200d300

# cat /sys/devices/platform/soc/ee160000.sd/mmc_host/mmc2/mmc2:0001 
1b534d3030303030103916141700f600
# dd if=/dev/mmcblk2 of=/dev/null bs=1M count=512 iflag=direct
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 56.7809 s, 9.5 MB/s

# grep sd /proc/interrupts
100:       2276          0     GIC-0 197 Level     ee100000.sd
101:       3040          0     GIC-0 199 Level     ee140000.sd
102:    2124012          0     GIC-0 200 Level     ee160000.sd
178:          0          0  e6053000.gpio  12 Edge      ee100000.sd cd
197:          0          0  e6054000.gpio  15 Edge      ee160000.sd cd

[PATCH/RFC 4/5] mmc: renesas_sdhi: add support for R-Car Gen3 SDHI DMAC

[Simon Horman]

R-Car Gen3 has a dedicated DMA controller for SDHI module. Since
the DMAC is in a part of SDHI module and is not suitable as dmaengine,
this patch adds a different code as tmio_mmc_dma_gen3.c.

Clearing of DM_CM_INFO1 after DMA thanks to Dirk Behme

Cc: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Ai Kyuse <ai.kyuse.uw@renesas.com>
---
 drivers/mmc/host/Kconfig                      |  17 ++
 drivers/mmc/host/Makefile                     |   8 +-
 drivers/mmc/host/renesas_sdhi_internal_dmac.c | 275 ++++++++++++++++++++++++++
 drivers/mmc/host/renesas_sdhi_sys_dmac.c      |   2 +-
 drivers/mmc/host/tmio_mmc.h                   |   1 +
 5 files changed, 301 insertions(+), 2 deletions(-)
 create mode 100644 drivers/mmc/host/renesas_sdhi_internal_dmac.c

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 5755b69f2f72..e813d420d7b3 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -575,10 +575,27 @@ config MMC_SDHI
 	depends on SUPERH || ARM || ARM64
 	depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
 	select MMC_TMIO_CORE
+	select MMC_SDHI_SYS_DMAC if (SUPERH || ARM)
+	select MMC_SDHI_INTERNAL_DMAC if ARM64
 	help
 	  This provides support for the SDHI SD/SDIO controller found in
 	  Renesas SuperH, ARM and ARM64 based SoCs
 
+config MMC_SDHI_SYS_DMAC
+	tristate "DMA support use of SYS DMAC with SDHI SD/SDIO controller"
+	depends on MMC_SDHI
+	help
+	  This provides DMA support for the SDHI SD/SDIO controller
+	  found in SuperH and Renesas ARM based SoCs.
+
+config MMC_SDHI_INTERNAL_DMAC
+	tristate "DMA support for Internal DMAC with SDHI SD/SDIO controller"
+	depends on ARM64 || COMPILE_TEST
+	depends on MMC_SDHI
+	help
+	  This provides DMA support for the SDHI SD/SDIO controller
+	  found in Renesas arm64 based SoCs.
+
 config MMC_CB710
 	tristate "ENE CB710 MMC/SD Interface support"
 	depends on PCI
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 4d4547116311..8c46766c000c 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -36,7 +36,13 @@ obj-$(CONFIG_MMC_S3C)   	+= s3cmci.o
 obj-$(CONFIG_MMC_SDRICOH_CS)	+= sdricoh_cs.o
 obj-$(CONFIG_MMC_TMIO)		+= tmio_mmc.o
 obj-$(CONFIG_MMC_TMIO_CORE)	+= tmio_mmc_core.o
-obj-$(CONFIG_MMC_SDHI)		+= renesas_sdhi_core.o renesas_sdhi_sys_dmac.o
+obj-$(CONFIG_MMC_SDHI)		+= renesas_sdhi_core.o
+ifeq ($(subst m,y,$(CONFIG_MMC_SDHI_SYS_DMAC)),y)
+obj-$(CONFIG_MMC_SDHI)		+= renesas_sdhi_sys_dmac.o
+endif
+ifeq ($(subst m,y,$(CONFIG_MMC_SDHI_INTERNAL_DMAC)),y)
+obj-$(CONFIG_MMC_SDHI)		+= renesas_sdhi_internal_dmac.o
+endif
 obj-$(CONFIG_MMC_CB710)		+= cb710-mmc.o
 obj-$(CONFIG_MMC_VIA_SDMMC)	+= via-sdmmc.o
 obj-$(CONFIG_SDH_BFIN)		+= bfin_sdh.o
diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
new file mode 100644
index 000000000000..a16b616a2c96
--- /dev/null
+++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
@@ -0,0 +1,275 @@
+/*
+ * DMA support for Internal DMAC with SDHI SD/SDIO controller
+ *
+ * Copyright (C) 2016-17 Renesas Electronics Corporation
+ * Copyright (C) 2016-17 Horms Solutions, Simon Horman
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/mfd/tmio.h>
+#include <linux/mmc/host.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/pagemap.h>
+#include <linux/scatterlist.h>
+
+#include "renesas_sdhi.h"
+#include "tmio_mmc.h"
+
+#define DM_CM_DTRAN_MODE	0x820
+#define DM_CM_DTRAN_CTRL	0x828
+#define DM_CM_RST		0x830
+#define DM_CM_INFO1		0x840
+#define DM_CM_INFO1_MASK	0x848
+#define DM_CM_INFO2		0x850
+#define DM_CM_INFO2_MASK	0x858
+#define DM_DTRAN_ADDR		0x880
+
+/* DM_CM_DTRAN_MODE */
+#define DTRAN_MODE_CH_NUM_CH0	0	/* "downstream" = for write commands */
+#define DTRAN_MODE_CH_NUM_CH1	BIT(16)	/* "uptream" = for read commands */
+#define DTRAN_MODE_BUS_WID_TH	(BIT(5) | BIT(4))
+#define DTRAN_MODE_ADDR_MODE	BIT(0)	/* 1 = Increment address */
+
+/* DM_CM_DTRAN_CTRL */
+#define DTRAN_CTRL_DM_START	BIT(0)
+
+/* DM_CM_RST */
+#define RST_DTRANRST1		BIT(9)
+#define RST_DTRANRST0		BIT(8)
+#define RST_RESERVED_BITS	GENMASK_ULL(32, 0)
+
+/* DM_CM_INFO1 and DM_CM_INFO1_MASK */
+#define INFO1_CLEAR		0
+#define INFO1_DTRANEND1		BIT(17)
+#define INFO1_DTRANEND0		BIT(16)
+
+/* DM_CM_INFO2 and DM_CM_INFO2_MASK */
+#define INFO2_DTRANERR1		BIT(17)
+#define INFO2_DTRANERR0		BIT(16)
+
+/*
+ * Specification of this driver:
+ * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma
+ * - Since this SDHI DMAC register set has actual 32-bit and "bus_shift" is 2,
+ *   this driver cannot use original sd_ctrl_{write,read}32 functions.
+ */
+
+/* Definitions for sampling clocks */
+static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
+	{
+		.clk_rate = 0,
+		.tap = 0x00000300,
+	},
+};
+
+static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
+	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE |
+			  TMIO_MMC_CLK_ACTUAL | TMIO_MMC_MIN_RCAR2,
+	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+			  MMC_CAP_CMD23,
+	.bus_shift	= 2,
+	.scc_offset	= 0x1000,
+	.taps		= rcar_gen3_scc_taps,
+	.taps_num	= ARRAY_SIZE(rcar_gen3_scc_taps),
+	/* Gen3 SDHI DMAC can handle 0xffffffff blk count, but seg = 1 */
+	.max_blk_count	= 0xffffffff,
+	.max_segs	= 1,
+};
+
+static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
+	{ .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
+	{ .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
+	{},
+};
+MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match);
+
+static void
+renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host,
+				    int addr, u64 val)
+{
+	writeq(val, host->ctl + addr);
+}
+
+static void
+renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable)
+{
+	if (!host->chan_tx || !host->chan_rx)
+		return;
+
+	if (!enable)
+		renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1,
+						    INFO1_CLEAR);
+
+	if (host->dma->enable)
+		host->dma->enable(host, enable);
+}
+
+static void
+renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) {
+	u64 val = RST_DTRANRST1 | RST_DTRANRST0;
+
+	renesas_sdhi_internal_dmac_enable_dma(host, false);
+
+	renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
+					    RST_RESERVED_BITS & ~val);
+	renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
+					    RST_RESERVED_BITS | val);
+
+	renesas_sdhi_internal_dmac_enable_dma(host, true);
+}
+
+static void
+renesas_sdhi_internal_dmac_complete_dma(struct tmio_mmc_host *host) {
+	tasklet_schedule(&host->dma_complete);
+}
+
+static void
+renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
+				     struct mmc_data *data)
+{
+	struct scatterlist *sg = host->sg_ptr;
+	u32 dtran_mode = DTRAN_MODE_BUS_WID_TH | DTRAN_MODE_ADDR_MODE;
+	enum dma_data_direction dir;
+	int ret;
+	u32 irq_mask;
+
+	/* This DMAC cannot handle if sg_len is not 1 */
+	WARN_ON(host->sg_len > 1);
+
+	/* This DMAC cannot handle if buffer is not 8-bytes alignment */
+	if (!IS_ALIGNED(sg->offset, 8)) {
+		host->force_pio = true;
+		renesas_sdhi_internal_dmac_enable_dma(host, false);
+		return;
+	}
+
+	if (data->flags & MMC_DATA_READ) {
+		dtran_mode |= DTRAN_MODE_CH_NUM_CH1;
+		dir = DMA_FROM_DEVICE;
+		irq_mask = TMIO_STAT_RXRDY;
+	} else {
+		dtran_mode |= DTRAN_MODE_CH_NUM_CH0;
+		dir = DMA_TO_DEVICE;
+		irq_mask = TMIO_STAT_TXRQ;
+	}
+
+	ret = dma_map_sg(&host->pdev->dev, sg, host->sg_len, dir);
+	if (ret < 0) {
+		dev_err(&host->pdev->dev, "%s: dma_map_sg failed\n", __func__);
+		return;
+	}
+
+	renesas_sdhi_internal_dmac_enable_dma(host, true);
+
+	/* disable PIO irqs to avoid "PIO IRQ in DMA mode!" */
+	tmio_mmc_disable_mmc_irqs(host, irq_mask);
+
+	/* set dma parameters */
+	renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE,
+					    dtran_mode);
+	renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR,
+					    sg->dma_address);
+}
+
+static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg)
+{
+	struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
+
+	tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
+
+	/* start the DMAC */
+	renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL,
+					    DTRAN_CTRL_DM_START);
+}
+
+static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg)
+{
+	struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
+	enum dma_data_direction dir;
+
+	spin_lock_irq(&host->lock);
+
+	if (!host->data)
+		goto out;
+
+	if (host->data->flags & MMC_DATA_READ)
+		dir = DMA_FROM_DEVICE;
+	else
+		dir = DMA_TO_DEVICE;
+
+	renesas_sdhi_internal_dmac_enable_dma(host, false);
+	dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->sg_len, dir);
+
+	spin_unlock_irq(&host->lock);
+
+	spin_lock_irq(&host->lock);
+	tmio_mmc_do_data_irq(host);
+out:
+	spin_unlock_irq(&host->lock);
+}
+
+static void
+renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host,
+				       struct tmio_mmc_data *pdata)
+{
+	/* Each value is set to non-zero to assume "enabling" each DMA */
+	host->chan_rx = host->chan_tx = (void *)0xdeadbeaf;
+
+	tasklet_init(&host->dma_complete,
+		     renesas_sdhi_internal_dmac_complete_tasklet_fn,
+		     (unsigned long)host);
+	tasklet_init(&host->dma_issue,
+		     renesas_sdhi_internal_dmac_issue_tasklet_fn,
+		     (unsigned long)host);
+}
+
+static void
+renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host)
+{
+	/* Each value is set to zero to assume "disabling" each DMA */
+	host->chan_rx = host->chan_tx = NULL;
+}
+
+static struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = {
+	.start = renesas_sdhi_internal_dmac_start_dma,
+	.enable = renesas_sdhi_internal_dmac_enable_dma,
+	.request = renesas_sdhi_internal_dmac_request_dma,
+	.release = renesas_sdhi_internal_dmac_release_dma,
+	.abort = renesas_sdhi_internal_dmac_abort_dma,
+	.complete = renesas_sdhi_internal_dmac_complete_dma,
+};
+
+static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev)
+{
+	return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops);
+}
+
+static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+				pm_runtime_force_resume)
+	SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
+			   tmio_mmc_host_runtime_resume,
+			   NULL)
+};
+
+static struct platform_driver renesas_internal_dmac_sdhi_driver = {
+	.driver		= {
+		.name	= "renesas_sdhi_internal_dmac",
+		.pm	= &renesas_sdhi_internal_dmac_dev_pm_ops,
+		.of_match_table = renesas_sdhi_internal_dmac_of_match,
+	},
+	.probe		= renesas_sdhi_internal_dmac_probe,
+	.remove		= renesas_sdhi_remove,
+};
+
+module_platform_driver(renesas_internal_dmac_sdhi_driver);
+
+MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC");
+MODULE_AUTHOR("Yoshihiro Shimoda");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
index 7eab55adc5b2..cc3e0f94b276 100644
--- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
@@ -1,5 +1,5 @@
 /*
- * DMA function for TMIO MMC implementations
+ * DMA support use of SYS DMAC with SDHI SD/SDIO controller
  *
  * Copyright (C) 2010-2011 Guennadi Liakhovetski
  *
diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h
index 82725f9de359..3b08c76a55e7 100644
--- a/drivers/mmc/host/tmio_mmc.h
+++ b/drivers/mmc/host/tmio_mmc.h
@@ -151,6 +151,7 @@ struct tmio_mmc_host {
 	struct dma_chan		*chan_rx;
 	struct dma_chan		*chan_tx;
 	struct completion	dma_dataend;
+	struct tasklet_struct	dma_complete;
 	struct tasklet_struct	dma_issue;
 	struct scatterlist	bounce_sg;
 	u8			*bounce_buf;
-- 
2.1.4