[PATCH mmc/next v2 0/4] mmc: renesas_sdhi: add support for R-Car Gen3 SDHI DMAC

[PATCH mmc/next v2 0/4] mmc: renesas_sdhi: add support for R-Car Gen3 SDHI DMAC

[Simon Horman]

Hi,

this series adds support for the internal DMAC used by r8a779[56] SoCs.
This is achieved by adding a new variant of the SDHI driver for this
DMA controller with compat strings for the r8a779[56] SoCs.
Compat strings for these SoCs are also removed from the existing SYS DMAC
variant of the SDHI driver.

Based on mmc/next

Headline performance boost: 9.5MB/s -> 39.7MB/s
Details below.

Changes since v1:
* Address review of v2 as noted in changelog of individual patches

Simon Horman (3):
  mmc: tmio, renesas-sdhi: add complete to DMA ops
  mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC
  mmc: renesas-sdhi: remove gen3 support from SYS-DMAC driver

Yoshihiro Shimoda (1):
  mmc: tmio, renesas-sdhi: add max_{segs,blk_count} to tmio_mmc_data

 drivers/mmc/host/Kconfig                      |  19 ++
 drivers/mmc/host/Makefile                     |   8 +-
 drivers/mmc/host/renesas_sdhi.h               |   2 +
 drivers/mmc/host/renesas_sdhi_core.c          |   2 +
 drivers/mmc/host/renesas_sdhi_internal_dmac.c | 275 ++++++++++++++++++++++++++
 drivers/mmc/host/renesas_sdhi_sys_dmac.c      |  29 +--
 drivers/mmc/host/tmio_mmc.h                   |   2 +
 drivers/mmc/host/tmio_mmc_core.c              |  16 +-
 include/linux/mfd/tmio.h                      |   2 +
 9 files changed, 327 insertions(+), 28 deletions(-)
 create mode 100644 drivers/mmc/host/renesas_sdhi_internal_dmac.c

-- 
2.1.4

Salvator-X/M3-W ES1.0
=====================

With Gen3 DMA Patches
---------------------

f97c698336e1 (topic/sdhi-gen3-dma-2017-v2) mmc: renesas-sdhi: remove gen3 support from SYS-DMAC driver

# dmesg | egrep '(sd|mmc)'
[    1.415083] sdhci: Secure Digital Host Controller Interface driver
[    1.421291] sdhci: Copyright(c) Pierre Ossman
[    1.426164] renesas_sdhi_internal_dmac ee100000.sd: Got CD GPIO
[    1.432123] renesas_sdhi_internal_dmac ee100000.sd: Got WP GPIO
[    1.559507] renesas_sdhi_internal_dmac ee140000.sd: mmc0 base at 0xee140000 max clock rate 200 MHz
[    1.568922] renesas_sdhi_internal_dmac ee160000.sd: Got CD GPIO
[    1.574928] renesas_sdhi_internal_dmac ee160000.sd: Got WP GPIO
[    1.589703] sdhci-pltfm: SDHCI platform and OF driver helper
[    1.638824] renesas_sdhi_internal_dmac ee100000.sd: Got CD GPIO
[    1.644806] renesas_sdhi_internal_dmac ee100000.sd: Got WP GPIO
[    1.771574] renesas_sdhi_internal_dmac ee100000.sd: mmc1 base at 0xee100000 max clock rate 200 MHz
[    1.781631] renesas_sdhi_internal_dmac ee160000.sd: Got CD GPIO
[    1.787624] renesas_sdhi_internal_dmac ee160000.sd: Got WP GPIO
[    1.844780] mmc0: new high speed MMC card at address 0001
[    1.851126] mmcblk0: mmc0:0001 eMMC   28.8 GiB
[    1.861040] mmcblk0boot0: mmc0:0001 eMMC   partition 1 4.00 MiB
[    1.871305] mmcblk0boot1: mmc0:0001 eMMC   partition 2 4.00 MiB
[    1.881414] mmcblk0rpmb: mmc0:0001 eMMC   partition 3 4.00 MiB
[    1.890595]  mmcblk0: p1
[    1.915609] renesas_sdhi_internal_dmac ee160000.sd: mmc2 base at 0xee160000 max clock rate 200 MHz
[    2.055552] mmc1: new ultra high speed SDR50 SDHC card at address e624
[    2.066569] mmcblk1: mmc1:e624 SU08G 7.40 GiB
[    2.081831]  mmcblk1: p1
[    2.275547] mmc2: new ultra high speed SDR50 SDHC card at address 0001
[    2.282419] mmcblk2: mmc2:0001 00000 29.8 GiB
[    2.296600]  mmcblk2: p1

# grep sd /proc/interrupts
100:        396          0     GIC-0 197 Level     ee100000.sd
101:        658          0     GIC-0 199 Level     ee140000.sd
102:        406          0     GIC-0 200 Level     ee160000.sd
178:          0          0  e6053000.gpio  12 Edge      ee100000.sd cd
197:          0          0  e6054000.gpio  15 Edge      ee160000.sd cd

# cat /sys/devices/platform/soc/ee100000.sd/mmc_host/mmc1/mmc1:*/cid
035344535530384780b1b8a11200d300
# dd if=/dev/mmcblk1 of=/dev/null bs=1M count=512 iflag=direct
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 13.5498 s, 39.6 MB/s

# cat /sys/devices/platform/soc/ee160000.sd/mmc_host/mmc2/mmc2:*/cid
1b534d3030303030103916141700f600
# dd if=/dev/mmcblk2 of=/dev/null bs=1M count=512 iflag=direct
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 17.5571 s, 30.6 MB/s

# grep sd /proc/interrupts
100:      24972          0     GIC-0 197 Level     ee100000.sd
101:        658          0     GIC-0 199 Level     ee140000.sd
102:      24982          0     GIC-0 200 Level     ee160000.sd
178:          0          0  e6053000.gpio  12 Edge      ee100000.sd cd
197:          0          0  e6054000.gpio  15 Edge      ee160000.sd cd

Without Gen3 DMA Patches
------------------------

f2cd281b9f7d (mmc/next) mmc: sdhci-pci: Enable card detect wake for Intel BYT-related SD controllers

# dmesg | egrep '(sd|mmc)'
[    1.413160] sdhci: Secure Digital Host Controller Interface driver
[    1.419368] sdhci: Copyright(c) Pierre Ossman
[    1.424317] sh_mobile_sdhi ee100000.sd: Got CD GPIO
[    1.429254] sh_mobile_sdhi ee100000.sd: Got WP GPIO
[    1.556994] sh_mobile_sdhi ee140000.sd: mmc0 base at 0xee140000 max clock rate 200 MHz
[    1.565359] sh_mobile_sdhi ee160000.sd: Got CD GPIO
[    1.570313] sh_mobile_sdhi ee160000.sd: Got WP GPIO
[    1.584078] sdhci-pltfm: SDHCI platform and OF driver helper
[    1.633385] sh_mobile_sdhi ee100000.sd: Got CD GPIO
[    1.638319] sh_mobile_sdhi ee100000.sd: Got WP GPIO
[    1.765061] sh_mobile_sdhi ee100000.sd: mmc1 base at 0xee100000 max clock rate 200 MHz
[    1.774258] sh_mobile_sdhi ee160000.sd: Got CD GPIO
[    1.779185] sh_mobile_sdhi ee160000.sd: Got WP GPIO
[    1.834292] mmc0: new high speed MMC card at address 0001
[    1.840594] mmcblk0: mmc0:0001 eMMC   28.8 GiB 
[    1.850501] mmcblk0boot0: mmc0:0001 eMMC   partition 1 4.00 MiB
[    1.860750] mmcblk0boot1: mmc0:0001 eMMC   partition 2 4.00 MiB
[    1.870834] mmcblk0rpmb: mmc0:0001 eMMC   partition 3 4.00 MiB
[    1.880344]  mmcblk0: p1
[    1.909078] sh_mobile_sdhi ee160000.sd: mmc2 base at 0xee160000 max clock rate 200 MHz
[    2.049028] mmc1: new ultra high speed SDR50 SDHC card at address e624
[    2.060070] mmcblk1: mmc1:e624 SU08G 7.40 GiB 
[    2.075628]  mmcblk1: p1
[    2.165019] mmc2: new ultra high speed SDR50 SDHC card at address 0001
[    2.175911] mmcblk2: mmc2:0001 00000 29.8 GiB 
[    2.190409]  mmcblk2: p1

# grep sd /proc/interrupts
100:       2276          0     GIC-0 197 Level     ee100000.sd
101:       2986          0     GIC-0 199 Level     ee140000.sd
102:       2276          0     GIC-0 200 Level     ee160000.sd
178:          0          0  e6053000.gpio  12 Edge      ee100000.sd cd
197:          0          0  e6054000.gpio  15 Edge      ee160000.sd cd

# cat /sys/devices/platform/soc/ee100000.sd/mmc_host/mmc1/mmc1:*/cid
035344535530384780b1b8a11200d300
# dd if=/dev/mmcblk2 of=/dev/null bs=1M count=512 iflag=direct
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 56.7595 s, 9.5 MB/s

# cat /sys/devices/platform/soc/ee160000.sd/mmc_host/mmc2/mmc2:*/cid
1b534d3030303030103916141700f600
# dd if=/dev/mmcblk2 of=/dev/null bs=1M count=512 iflag=direct
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 56.7595 s, 9.5 MB/s

# grep sd /proc/interrupts
100:       2276          0     GIC-0 197 Level     ee100000.sd
101:       2986          0     GIC-0 199 Level     ee140000.sd
102:    2124004          0     GIC-0 200 Level     ee160000.sd
178:          0          0  e6053000.gpio  12 Edge      ee100000.sd cd
197:          0          0  e6054000.gpio  15 Edge      ee160000.sd cd


Lager/H2 ES2.0
==============

With Gen3 DMA Patches
---------------------

f97c698336e1 (topic/sdhi-gen3-dma-2017-v2) mmc: renesas-sdhi: remove gen3 support from SYS-DMAC driver

# dmesg | egrep '(sd|mmc)'
[    2.311352] sh_mobile_sdhi ee100000.sd: Got CD GPIO
[    2.316918] sh_mobile_sdhi ee140000.sd: Got CD GPIO
[    2.375558] sh_mmcif ee220000.mmc: Chip version 0x0003, clock rate 12MHz
[    2.482338] sh_mobile_sdhi ee100000.sd: Got CD GPIO
[    2.695677] sh_mobile_sdhi ee100000.sd: mmc1 base at 0xee100000 max clock rate 195 MHz
[    2.704157] sh_mobile_sdhi ee140000.sd: Got CD GPIO
[    2.773828] mmc0: new high speed MMC card at address 0001
[    2.779650] mmcblk0: mmc0:0001 MMC08G 7.33 GiB
[    2.784388] mmcblk0boot0: mmc0:0001 MMC08G partition 1 2.00 MiB
[    2.790544] mmcblk0boot1: mmc0:0001 MMC08G partition 2 2.00 MiB
[    2.798218]  mmcblk0: p1
[    2.917476] sh_mobile_sdhi ee140000.sd: mmc2 base at 0xee140000 max clock rate 97 MHz
[    3.142783] mmc1: new ultra high speed SDR104 SDHC card at address 0001
[    3.149772] mmcblk1: mmc1:0001 00000 29.8 GiB
[    3.163596]  mmcblk1: p1
[    3.335665] mmc2: new ultra high speed SDR50 SDHC card at address 0001
[    3.342532] mmcblk2: mmc2:0001 00000 29.8 GiB
[    3.356495]  mmcblk2: p1

# grep sd /proc/interrupts
 99:        572          0          0          0     GIC-0 197 Level     ee100000.sd
100:        540          0          0          0     GIC-0 199 Level     ee140000.sd
220:          0          0          0          0  e6053000.gpio   6 Edge      ee100000.sd cd
236:          0          0          0          0  e6053000.gpio  22 Edge      ee140000.sd cd

# cat /sys/devices/platform/ee100000.sd/mmc_host/mmc1/mmc1:*/cid
1b534d303030303010ed85537600fc00
# dd if=/dev/mmcblk1 of=/dev/null bs=1M count=512 iflag=direct
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 14.5833 s, 36.8 MB/s

# cat /sys/devices/platform/ee140000.sd/mmc_host/mmc2/mmc2:*/cid
1b534d303030303010f0c957f500fc00
# dd if=/dev/mmcblk2 of=/dev/null bs=1M count=512 iflag=direct
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 18.8682 s, 28.5 MB/s

(above dd for mmcblk2 was run twice)

# grep sd /proc/interrupts
 99:      12860          0          0          0     GIC-0 197 Level     ee100000.sd
100:      12828          0          0          0     GIC-0 199 Level     ee140000.sd
220:          0          0          0          0  e6053000.gpio   6 Edge      ee100000.sd cd
236:          0          0          0          0  e6053000.gpio  22 Edge      ee140000.sd cd

Without Gen3 DMA Patches
------------------------

f2cd281b9f7d (mmc/next) mmc: sdhci-pci: Enable card detect wake for Intel BYT-related SD controllers

# dmesg | egrep '(sd|mmc)'
[    2.310760] sh_mobile_sdhi ee100000.sd: Got CD GPIO
[    2.316185] sh_mobile_sdhi ee140000.sd: Got CD GPIO
[    2.375581] sh_mmcif ee220000.mmc: Chip version 0x0003, clock rate 12MHz
[    2.482371] sh_mobile_sdhi ee100000.sd: Got CD GPIO
[    2.695738] sh_mobile_sdhi ee100000.sd: mmc1 base at 0xee100000 max clock rate 195 MHz
[    2.704210] sh_mobile_sdhi ee140000.sd: Got CD GPIO
[    2.784707] mmc0: new high speed MMC card at address 0001
[    2.790501] mmcblk0: mmc0:0001 MMC08G 7.33 GiB
[    2.795219] mmcblk0boot0: mmc0:0001 MMC08G partition 1 2.00 MiB
[    2.804059] mmcblk0boot1: mmc0:0001 MMC08G partition 2 2.00 MiB
[    2.811731]  mmcblk0: p1
[    2.915727] sh_mobile_sdhi ee140000.sd: mmc2 base at 0xee140000 max clock rate 97 MHz
[    3.122796] mmc1: new ultra high speed SDR104 SDHC card at address 0001
[    3.129798] mmcblk1: mmc1:0001 00000 29.8 GiB
[    3.143603]  mmcblk1: p1
[    3.335704] mmc2: new ultra high speed SDR50 SDHC card at address 0001
[    3.342565] mmcblk2: mmc2:0001 00000 29.8 GiB
[    3.356510]  mmcblk2: p1

# grep sd /proc/interrupts
 99:        572          0          0          0     GIC-0 197 Level     ee100000.sd
100:        538          0          0          0     GIC-0 199 Level     ee140000.sd
220:          0          0          0          0  e6053000.gpio   6 Edge      ee100000.sd cd
236:          0          0          0          0  e6053000.gpio  22 Edge      ee140000.sd cd

# cat /sys/devices/platform/ee100000.sd/mmc_host/mmc1/mmc1:*/cid
1b534d303030303010ed85537600fc00
# dd if=/dev/mmcblk1 of=/dev/null bs=1M count=512 iflag=direct
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 14.6023 s, 36.8 MB/s

# cat /sys/devices/platform/ee140000.sd/mmc_host/mmc2/mmc2:*/cid
1b534d303030303010f0c957f500fc00
# dd if=/dev/mmcblk2 of=/dev/null bs=1M count=512 iflag=direct
512+0 records in
512+0 records out
536870912 bytes (537 MB) copied, 18.8882 s, 28.4 MB/s

# grep sd /proc/interrupts
 99:      12860          0          0          0     GIC-0 197 Level     ee100000.sd
100:      12826          0          0          0     GIC-0 199 Level     ee140000.sd
220:          0          0          0          0  e6053000.gpio   6 Edge      ee100000.sd cd
236:          0          0          0          0  e6053000.gpio  22 Edge      ee140000.sd cd

[PATCH mmc/next v2 1/4] mmc: tmio, renesas-sdhi: add max_{segs,blk_count} to tmio_mmc_data

[Simon Horman]

From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Allow TMIO and SDHI driver implementations to provide values for
max_segs and max_blk_count.

A follow-up patch will set these values for Renesas Gen3 SoCs
the using an SDHI driver.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Ai Kyuse <ai.kyuse.uw@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
v2
* Enhanced changelog
* Include Renesas SDHI changes
---
 drivers/mmc/host/renesas_sdhi.h      | 2 ++
 drivers/mmc/host/renesas_sdhi_core.c | 2 ++
 drivers/mmc/host/tmio_mmc_core.c     | 6 +++---
 include/linux/mfd/tmio.h             | 2 ++
 4 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdhi.h
index eb3ea15ff92d..6f7233fe32a2 100644
--- a/drivers/mmc/host/renesas_sdhi.h
+++ b/drivers/mmc/host/renesas_sdhi.h
@@ -31,6 +31,8 @@ struct renesas_sdhi_of_data {
 	int scc_offset;
 	struct renesas_sdhi_scc *taps;
 	int taps_num;
+	unsigned int max_blk_count;
+	unsigned short max_segs;
 };
 
 int renesas_sdhi_probe(struct platform_device *pdev,
diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
index f4690cba3443..75c7bf4f7ca2 100644
--- a/drivers/mmc/host/renesas_sdhi_core.c
+++ b/drivers/mmc/host/renesas_sdhi_core.c
@@ -523,6 +523,8 @@ int renesas_sdhi_probe(struct platform_device *pdev,
 		mmc_data->capabilities |= of_data->capabilities;
 		mmc_data->capabilities2 |= of_data->capabilities2;
 		mmc_data->dma_rx_offset = of_data->dma_rx_offset;
+		mmc_data->max_blk_count = of_data->max_blk_count;
+		mmc_data->max_segs = of_data->max_segs;
 		dma_priv->dma_buswidth = of_data->dma_buswidth;
 		host->bus_shift = of_data->bus_shift;
 	}
diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
index fbe38464e7d7..7cb8d3510396 100644
--- a/drivers/mmc/host/tmio_mmc_core.c
+++ b/drivers/mmc/host/tmio_mmc_core.c
@@ -1248,10 +1248,10 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host,
 
 	mmc->caps |= MMC_CAP_4_BIT_DATA | pdata->capabilities;
 	mmc->caps2 |= pdata->capabilities2;
-	mmc->max_segs = 32;
+	mmc->max_segs = pdata->max_segs ? : 32;
 	mmc->max_blk_size = 512;
-	mmc->max_blk_count = (PAGE_SIZE / mmc->max_blk_size) *
-		mmc->max_segs;
+	mmc->max_blk_count = pdata->max_blk_count ? :
+		(PAGE_SIZE / mmc->max_blk_size) * mmc->max_segs;
 	mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
 	mmc->max_seg_size = mmc->max_req_size;
 
diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h
index c83c16b931a8..4e261ea94d6a 100644
--- a/include/linux/mfd/tmio.h
+++ b/include/linux/mfd/tmio.h
@@ -128,6 +128,8 @@ struct tmio_mmc_data {
 	unsigned int			cd_gpio;
 	int				alignment_shift;
 	dma_addr_t			dma_rx_offset;
+	unsigned int			max_blk_count;
+	unsigned short			max_segs;
 	void (*set_pwr)(struct platform_device *host, int state);
 	void (*set_clk_div)(struct platform_device *host, int state);
 };
-- 
2.1.4

[PATCH mmc/next v2 2/4] mmc: tmio, renesas-sdhi: add complete to DMA ops

[Simon Horman]

Add complete to DMA ops to allow DMAC implementation dependent
handling of DMA completion.

Also implement the operation for SDHI.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
v2
* Implement operation for SDHI to avoid regression
---
 drivers/mmc/host/renesas_sdhi_sys_dmac.c |  6 ++++++
 drivers/mmc/host/tmio_mmc.h              |  1 +
 drivers/mmc/host/tmio_mmc_core.c         | 10 ++++++++--
 3 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
index 202cf4346fdf..7a85610525b0 100644
--- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
@@ -127,6 +127,11 @@ static void renesas_sdhi_sys_dmac_abort_dma(struct tmio_mmc_host *host)
 	renesas_sdhi_sys_dmac_enable_dma(host, true);
 }
 
+static void renesas_sdhi_sys_dmac_complete_dma(struct tmio_mmc_host *host)
+{
+	complete(&host->dma_dataend);
+}
+
 static void renesas_sdhi_sys_dmac_dma_callback(void *arg)
 {
 	struct tmio_mmc_host *host = arg;
@@ -448,6 +453,7 @@ static const struct tmio_mmc_dma_ops renesas_sdhi_sys_dmac_dma_ops = {
 	.request = renesas_sdhi_sys_dmac_request_dma,
 	.release = renesas_sdhi_sys_dmac_release_dma,
 	.abort = renesas_sdhi_sys_dmac_abort_dma,
+	.complete = renesas_sdhi_sys_dmac_complete_dma,
 };
 
 static int renesas_sdhi_sys_dmac_probe(struct platform_device *pdev)
diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h
index 768c8abaedda..89f0e264f02f 100644
--- a/drivers/mmc/host/tmio_mmc.h
+++ b/drivers/mmc/host/tmio_mmc.h
@@ -122,6 +122,7 @@ struct tmio_mmc_dma_ops {
 			struct tmio_mmc_data *pdata);
 	void (*release)(struct tmio_mmc_host *host);
 	void (*abort)(struct tmio_mmc_host *host);
+	void (*complete)(struct tmio_mmc_host *host);
 };
 
 struct tmio_mmc_host {
diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
index 7cb8d3510396..b65111cc8a17 100644
--- a/drivers/mmc/host/tmio_mmc_core.c
+++ b/drivers/mmc/host/tmio_mmc_core.c
@@ -87,6 +87,12 @@ static inline void tmio_mmc_abort_dma(struct tmio_mmc_host *host)
 		host->dma_ops->abort(host);
 }
 
+static inline void tmio_mmc_complete_dma(struct tmio_mmc_host *host)
+{
+	if (host->dma_ops)
+		host->dma_ops->complete(host);
+}
+
 void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
 {
 	host->sdcard_irq_mask &= ~(i & TMIO_MASK_IRQ);
@@ -605,11 +611,11 @@ static void tmio_mmc_data_irq(struct tmio_mmc_host *host, unsigned int stat)
 
 		if (done) {
 			tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
-			complete(&host->dma_dataend);
+			tmio_mmc_complete_dma(host);
 		}
 	} else if (host->chan_rx && (data->flags & MMC_DATA_READ) && !host->force_pio) {
 		tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
-		complete(&host->dma_dataend);
+		tmio_mmc_complete_dma(host);
 	} else {
 		tmio_mmc_do_data_irq(host);
 		tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_READOP | TMIO_MASK_WRITEOP);
-- 
2.1.4

[PATCH mmc/next v2 3/4] mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC

[Simon Horman]

Add a new variant of the SDHI driver to support R-Car Gen3 with DMA via
on-chip bus mastering.  Since the DMAC is in a part of the SDHI module it
is not suitable to be used via DMA Engine.

Clearing of DM_CM_INFO1 after DMA thanks to Dirk Behme

Cc: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Ai Kyuse <ai.kyuse.uw@renesas.com>
---
v2
* Enhanced help text and changelog
---
 drivers/mmc/host/Kconfig                      |  19 ++
 drivers/mmc/host/Makefile                     |   8 +-
 drivers/mmc/host/renesas_sdhi_internal_dmac.c | 275 ++++++++++++++++++++++++++
 drivers/mmc/host/renesas_sdhi_sys_dmac.c      |   2 +-
 drivers/mmc/host/tmio_mmc.h                   |   1 +
 5 files changed, 303 insertions(+), 2 deletions(-)
 create mode 100644 drivers/mmc/host/renesas_sdhi_internal_dmac.c

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 5755b69f2f72..81c81ed19735 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -575,10 +575,29 @@ config MMC_SDHI
 	depends on SUPERH || ARM || ARM64
 	depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
 	select MMC_TMIO_CORE
+	select MMC_SDHI_SYS_DMAC if (SUPERH || ARM)
+	select MMC_SDHI_INTERNAL_DMAC if ARM64
 	help
 	  This provides support for the SDHI SD/SDIO controller found in
 	  Renesas SuperH, ARM and ARM64 based SoCs
 
+config MMC_SDHI_SYS_DMAC
+	tristate "DMA for SDHI SD/SDIO controllers using SYS-DMAC"
+	depends on MMC_SDHI
+	help
+	  This provides DMA support for SDHI SD/SDIO controllers
+	  using SYS-DMAC via DMA Engine. This supports the controllers
+	  found in SuperH and Renesas ARM based SoCs.
+
+config MMC_SDHI_INTERNAL_DMAC
+	tristate "DMA for SDHI SD/SDIO controllers using on-chip bus mastering"
+	depends on ARM64 || COMPILE_TEST
+	depends on MMC_SDHI
+	help
+	  This provides DMA support for SDHI SD/SDIO controllers
+	  using on-chip bus mastering. This supports the controllers
+	  found in arm64 based SoCs.
+
 config MMC_CB710
 	tristate "ENE CB710 MMC/SD Interface support"
 	depends on PCI
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 4d4547116311..8c46766c000c 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -36,7 +36,13 @@ obj-$(CONFIG_MMC_S3C)   	+= s3cmci.o
 obj-$(CONFIG_MMC_SDRICOH_CS)	+= sdricoh_cs.o
 obj-$(CONFIG_MMC_TMIO)		+= tmio_mmc.o
 obj-$(CONFIG_MMC_TMIO_CORE)	+= tmio_mmc_core.o
-obj-$(CONFIG_MMC_SDHI)		+= renesas_sdhi_core.o renesas_sdhi_sys_dmac.o
+obj-$(CONFIG_MMC_SDHI)		+= renesas_sdhi_core.o
+ifeq ($(subst m,y,$(CONFIG_MMC_SDHI_SYS_DMAC)),y)
+obj-$(CONFIG_MMC_SDHI)		+= renesas_sdhi_sys_dmac.o
+endif
+ifeq ($(subst m,y,$(CONFIG_MMC_SDHI_INTERNAL_DMAC)),y)
+obj-$(CONFIG_MMC_SDHI)		+= renesas_sdhi_internal_dmac.o
+endif
 obj-$(CONFIG_MMC_CB710)		+= cb710-mmc.o
 obj-$(CONFIG_MMC_VIA_SDMMC)	+= via-sdmmc.o
 obj-$(CONFIG_SDH_BFIN)		+= bfin_sdh.o
diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
new file mode 100644
index 000000000000..a16b616a2c96
--- /dev/null
+++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
@@ -0,0 +1,275 @@
+/*
+ * DMA support for Internal DMAC with SDHI SD/SDIO controller
+ *
+ * Copyright (C) 2016-17 Renesas Electronics Corporation
+ * Copyright (C) 2016-17 Horms Solutions, Simon Horman
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/mfd/tmio.h>
+#include <linux/mmc/host.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/pagemap.h>
+#include <linux/scatterlist.h>
+
+#include "renesas_sdhi.h"
+#include "tmio_mmc.h"
+
+#define DM_CM_DTRAN_MODE	0x820
+#define DM_CM_DTRAN_CTRL	0x828
+#define DM_CM_RST		0x830
+#define DM_CM_INFO1		0x840
+#define DM_CM_INFO1_MASK	0x848
+#define DM_CM_INFO2		0x850
+#define DM_CM_INFO2_MASK	0x858
+#define DM_DTRAN_ADDR		0x880
+
+/* DM_CM_DTRAN_MODE */
+#define DTRAN_MODE_CH_NUM_CH0	0	/* "downstream" = for write commands */
+#define DTRAN_MODE_CH_NUM_CH1	BIT(16)	/* "uptream" = for read commands */
+#define DTRAN_MODE_BUS_WID_TH	(BIT(5) | BIT(4))
+#define DTRAN_MODE_ADDR_MODE	BIT(0)	/* 1 = Increment address */
+
+/* DM_CM_DTRAN_CTRL */
+#define DTRAN_CTRL_DM_START	BIT(0)
+
+/* DM_CM_RST */
+#define RST_DTRANRST1		BIT(9)
+#define RST_DTRANRST0		BIT(8)
+#define RST_RESERVED_BITS	GENMASK_ULL(32, 0)
+
+/* DM_CM_INFO1 and DM_CM_INFO1_MASK */
+#define INFO1_CLEAR		0
+#define INFO1_DTRANEND1		BIT(17)
+#define INFO1_DTRANEND0		BIT(16)
+
+/* DM_CM_INFO2 and DM_CM_INFO2_MASK */
+#define INFO2_DTRANERR1		BIT(17)
+#define INFO2_DTRANERR0		BIT(16)
+
+/*
+ * Specification of this driver:
+ * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma
+ * - Since this SDHI DMAC register set has actual 32-bit and "bus_shift" is 2,
+ *   this driver cannot use original sd_ctrl_{write,read}32 functions.
+ */
+
+/* Definitions for sampling clocks */
+static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
+	{
+		.clk_rate = 0,
+		.tap = 0x00000300,
+	},
+};
+
+static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
+	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE |
+			  TMIO_MMC_CLK_ACTUAL | TMIO_MMC_MIN_RCAR2,
+	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+			  MMC_CAP_CMD23,
+	.bus_shift	= 2,
+	.scc_offset	= 0x1000,
+	.taps		= rcar_gen3_scc_taps,
+	.taps_num	= ARRAY_SIZE(rcar_gen3_scc_taps),
+	/* Gen3 SDHI DMAC can handle 0xffffffff blk count, but seg = 1 */
+	.max_blk_count	= 0xffffffff,
+	.max_segs	= 1,
+};
+
+static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
+	{ .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
+	{ .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
+	{},
+};
+MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match);
+
+static void
+renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host,
+				    int addr, u64 val)
+{
+	writeq(val, host->ctl + addr);
+}
+
+static void
+renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable)
+{
+	if (!host->chan_tx || !host->chan_rx)
+		return;
+
+	if (!enable)
+		renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1,
+						    INFO1_CLEAR);
+
+	if (host->dma->enable)
+		host->dma->enable(host, enable);
+}
+
+static void
+renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) {
+	u64 val = RST_DTRANRST1 | RST_DTRANRST0;
+
+	renesas_sdhi_internal_dmac_enable_dma(host, false);
+
+	renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
+					    RST_RESERVED_BITS & ~val);
+	renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
+					    RST_RESERVED_BITS | val);
+
+	renesas_sdhi_internal_dmac_enable_dma(host, true);
+}
+
+static void
+renesas_sdhi_internal_dmac_complete_dma(struct tmio_mmc_host *host) {
+	tasklet_schedule(&host->dma_complete);
+}
+
+static void
+renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
+				     struct mmc_data *data)
+{
+	struct scatterlist *sg = host->sg_ptr;
+	u32 dtran_mode = DTRAN_MODE_BUS_WID_TH | DTRAN_MODE_ADDR_MODE;
+	enum dma_data_direction dir;
+	int ret;
+	u32 irq_mask;
+
+	/* This DMAC cannot handle if sg_len is not 1 */
+	WARN_ON(host->sg_len > 1);
+
+	/* This DMAC cannot handle if buffer is not 8-bytes alignment */
+	if (!IS_ALIGNED(sg->offset, 8)) {
+		host->force_pio = true;
+		renesas_sdhi_internal_dmac_enable_dma(host, false);
+		return;
+	}
+
+	if (data->flags & MMC_DATA_READ) {
+		dtran_mode |= DTRAN_MODE_CH_NUM_CH1;
+		dir = DMA_FROM_DEVICE;
+		irq_mask = TMIO_STAT_RXRDY;
+	} else {
+		dtran_mode |= DTRAN_MODE_CH_NUM_CH0;
+		dir = DMA_TO_DEVICE;
+		irq_mask = TMIO_STAT_TXRQ;
+	}
+
+	ret = dma_map_sg(&host->pdev->dev, sg, host->sg_len, dir);
+	if (ret < 0) {
+		dev_err(&host->pdev->dev, "%s: dma_map_sg failed\n", __func__);
+		return;
+	}
+
+	renesas_sdhi_internal_dmac_enable_dma(host, true);
+
+	/* disable PIO irqs to avoid "PIO IRQ in DMA mode!" */
+	tmio_mmc_disable_mmc_irqs(host, irq_mask);
+
+	/* set dma parameters */
+	renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE,
+					    dtran_mode);
+	renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR,
+					    sg->dma_address);
+}
+
+static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg)
+{
+	struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
+
+	tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
+
+	/* start the DMAC */
+	renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL,
+					    DTRAN_CTRL_DM_START);
+}
+
+static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg)
+{
+	struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
+	enum dma_data_direction dir;
+
+	spin_lock_irq(&host->lock);
+
+	if (!host->data)
+		goto out;
+
+	if (host->data->flags & MMC_DATA_READ)
+		dir = DMA_FROM_DEVICE;
+	else
+		dir = DMA_TO_DEVICE;
+
+	renesas_sdhi_internal_dmac_enable_dma(host, false);
+	dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->sg_len, dir);
+
+	spin_unlock_irq(&host->lock);
+
+	spin_lock_irq(&host->lock);
+	tmio_mmc_do_data_irq(host);
+out:
+	spin_unlock_irq(&host->lock);
+}
+
+static void
+renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host,
+				       struct tmio_mmc_data *pdata)
+{
+	/* Each value is set to non-zero to assume "enabling" each DMA */
+	host->chan_rx = host->chan_tx = (void *)0xdeadbeaf;
+
+	tasklet_init(&host->dma_complete,
+		     renesas_sdhi_internal_dmac_complete_tasklet_fn,
+		     (unsigned long)host);
+	tasklet_init(&host->dma_issue,
+		     renesas_sdhi_internal_dmac_issue_tasklet_fn,
+		     (unsigned long)host);
+}
+
+static void
+renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host)
+{
+	/* Each value is set to zero to assume "disabling" each DMA */
+	host->chan_rx = host->chan_tx = NULL;
+}
+
+static struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = {
+	.start = renesas_sdhi_internal_dmac_start_dma,
+	.enable = renesas_sdhi_internal_dmac_enable_dma,
+	.request = renesas_sdhi_internal_dmac_request_dma,
+	.release = renesas_sdhi_internal_dmac_release_dma,
+	.abort = renesas_sdhi_internal_dmac_abort_dma,
+	.complete = renesas_sdhi_internal_dmac_complete_dma,
+};
+
+static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev)
+{
+	return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops);
+}
+
+static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+				pm_runtime_force_resume)
+	SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
+			   tmio_mmc_host_runtime_resume,
+			   NULL)
+};
+
+static struct platform_driver renesas_internal_dmac_sdhi_driver = {
+	.driver		= {
+		.name	= "renesas_sdhi_internal_dmac",
+		.pm	= &renesas_sdhi_internal_dmac_dev_pm_ops,
+		.of_match_table = renesas_sdhi_internal_dmac_of_match,
+	},
+	.probe		= renesas_sdhi_internal_dmac_probe,
+	.remove		= renesas_sdhi_remove,
+};
+
+module_platform_driver(renesas_internal_dmac_sdhi_driver);
+
+MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC");
+MODULE_AUTHOR("Yoshihiro Shimoda");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
index 7a85610525b0..d1cfc2370915 100644
--- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
@@ -1,5 +1,5 @@
 /*
- * DMA function for TMIO MMC implementations
+ * DMA support use of SYS DMAC with SDHI SD/SDIO controller
  *
  * Copyright (C) 2016-17 Renesas Electronics Corporation
  * Copyright (C) 2016-17 Sang Engineering, Wolfram Sang
diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h
index 89f0e264f02f..bc562b141878 100644
--- a/drivers/mmc/host/tmio_mmc.h
+++ b/drivers/mmc/host/tmio_mmc.h
@@ -152,6 +152,7 @@ struct tmio_mmc_host {
 	struct dma_chan		*chan_rx;
 	struct dma_chan		*chan_tx;
 	struct completion	dma_dataend;
+	struct tasklet_struct	dma_complete;
 	struct tasklet_struct	dma_issue;
 	struct scatterlist	bounce_sg;
 	u8			*bounce_buf;
-- 
2.1.4

[PATCH mmc/next v2 4/4] mmc: renesas-sdhi: remove gen3 support from SYS-DMAC driver

[Simon Horman]

Gen3 SoCs are now supported by the internal DMAC variant of the SDHI driver.
Remove them from the SYS-DMAC variant where only PIO mode is supported
for those SoCs.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
v2
* Revised changelog
---
 drivers/mmc/host/renesas_sdhi_sys_dmac.c | 21 ---------------------
 1 file changed, 21 deletions(-)

diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
index d1cfc2370915..2897ee0b444a 100644
--- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
@@ -66,25 +66,6 @@ static const struct renesas_sdhi_of_data of_rcar_gen2_compatible = {
 	.taps_num	= ARRAY_SIZE(rcar_gen2_scc_taps),
 };
 
-/* Definitions for sampling clocks */
-static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
-	{
-		.clk_rate = 0,
-		.tap = 0x00000300,
-	},
-};
-
-static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
-	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE |
-			  TMIO_MMC_CLK_ACTUAL | TMIO_MMC_MIN_RCAR2,
-	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
-			  MMC_CAP_CMD23,
-	.bus_shift	= 2,
-	.scc_offset	= 0x1000,
-	.taps		= rcar_gen3_scc_taps,
-	.taps_num	= ARRAY_SIZE(rcar_gen3_scc_taps),
-};
-
 static const struct of_device_id renesas_sdhi_sys_dmac_of_match[] = {
 	{ .compatible = "renesas,sdhi-shmobile" },
 	{ .compatible = "renesas,sdhi-sh73a0", .data = &of_default_cfg, },
@@ -98,8 +79,6 @@ static const struct of_device_id renesas_sdhi_sys_dmac_of_match[] = {
 	{ .compatible = "renesas,sdhi-r8a7792", .data = &of_rcar_gen2_compatible, },
 	{ .compatible = "renesas,sdhi-r8a7793", .data = &of_rcar_gen2_compatible, },
 	{ .compatible = "renesas,sdhi-r8a7794", .data = &of_rcar_gen2_compatible, },
-	{ .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
-	{ .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
 	{},
 };
 MODULE_DEVICE_TABLE(of, renesas_sdhi_sys_dmac_of_match);
-- 
2.1.4

Re: [PATCH mmc/next v2 3/4] mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 1387 bytes --]

On Fri, Jun 16, 2017 at 11:58:53AM +0200, Simon Horman wrote:
> Add a new variant of the SDHI driver to support R-Car Gen3 with DMA via
> on-chip bus mastering.  Since the DMAC is in a part of the SDHI module it
> is not suitable to be used via DMA Engine.
> 
> Clearing of DM_CM_INFO1 after DMA thanks to Dirk Behme
> 
> Cc: Dirk Behme <dirk.behme@de.bosch.com>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> Signed-off-by: Ai Kyuse <ai.kyuse.uw@renesas.com>

Your Sob is missing!

> + * - Since this SDHI DMAC register set has actual 32-bit and "bus_shift" is 2,
> + *   this driver cannot use original sd_ctrl_{write,read}32 functions.

Easier to understand, I'd think, would be:

Since the SDHI DMAC register set has not 16 but 32-bit width, we need a
custom accessor.

> +	ret = dma_map_sg(&host->pdev->dev, sg, host->sg_len, dir);
> +	if (ret < 0) {
> +		dev_err(&host->pdev->dev, "%s: dma_map_sg failed\n", __func__);

__func__?

> +	/* start the DMAC */

Not very useful comment in my book, but no strong opinion.

> +	renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL,
> +					    DTRAN_CTRL_DM_START);
> +}
> +	dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->sg_len, dir);
> +
> +	spin_unlock_irq(&host->lock);
> +
> +	spin_lock_irq(&host->lock);

Just keep the lock?

Rest looks good so far...


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Re: [PATCH mmc/next v2 1/4] mmc: tmio, renesas-sdhi: add max_{segs,blk_count} to tmio_mmc_data

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 580 bytes --]

On Fri, Jun 16, 2017 at 11:58:51AM +0200, Simon Horman wrote:
> From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> 
> Allow TMIO and SDHI driver implementations to provide values for
> max_segs and max_blk_count.
> 
> A follow-up patch will set these values for Renesas Gen3 SoCs
> the using an SDHI driver.
> 
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> Signed-off-by: Ai Kyuse <ai.kyuse.uw@renesas.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>


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Re: [PATCH mmc/next v2 2/4] mmc: tmio, renesas-sdhi: add complete to DMA ops

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 731 bytes --]

On Fri, Jun 16, 2017 at 11:58:52AM +0200, Simon Horman wrote:
> Add complete to DMA ops to allow DMAC implementation dependent
> handling of DMA completion.
> 
> Also implement the operation for SDHI.
> 
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Codewise, I am all fine with this patch. There is one naming, however:

> +	void (*complete)(struct tmio_mmc_host *host);

I'd rather call it 'dataend'. For internal DMAC, it is the same. But for
SYS-DMAC there is difference between DATAEND and DMA_COMPLETE. This is
exactly the reason we have commit 52ad9a8e854ca1 ("mmc: tmio: ensure end
of DMA and SD access are in sync").

Basically, something like %s/complete/dataend/g would do it for me...


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Re: [PATCH mmc/next v2 4/4] mmc: renesas-sdhi: remove gen3 support from SYS-DMAC driver

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 366 bytes --]

On Fri, Jun 16, 2017 at 11:58:54AM +0200, Simon Horman wrote:
> Gen3 SoCs are now supported by the internal DMAC variant of the SDHI driver.
> Remove them from the SYS-DMAC variant where only PIO mode is supported
> for those SoCs.
> 
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>


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Re: [PATCH mmc/next v2 0/4] mmc: renesas_sdhi: add support for R-Car Gen3 SDHI DMAC

[Wolfram Sang]

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> Based on mmc/next
> 
> Headline performance boost: 9.5MB/s -> 39.7MB/s

Did you test writing as well? For me, this fails on M3-W with CMD12
timeouts. We had some changes in CMD12 handling recently, so it might be
because of that. I'll check on Monday.

Visual code review follows...

Have a nice weekend all,

   Wolfram


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Re: [PATCH mmc/next v2 3/4] mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC

[Simon Horman]

On Fri, Jun 16, 2017 at 11:58:53AM +0200, Simon Horman wrote:
> Add a new variant of the SDHI driver to support R-Car Gen3 with DMA via
> on-chip bus mastering.  Since the DMAC is in a part of the SDHI module it
> is not suitable to be used via DMA Engine.
> 
> Clearing of DM_CM_INFO1 after DMA thanks to Dirk Behme
> 
> Cc: Dirk Behme <dirk.behme@de.bosch.com>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> Signed-off-by: Ai Kyuse <ai.kyuse.uw@renesas.com>
> ---
> v2
> * Enhanced help text and changelog
> ---
>  drivers/mmc/host/Kconfig                      |  19 ++
>  drivers/mmc/host/Makefile                     |   8 +-
>  drivers/mmc/host/renesas_sdhi_internal_dmac.c | 275 ++++++++++++++++++++++++++
>  drivers/mmc/host/renesas_sdhi_sys_dmac.c      |   2 +-
>  drivers/mmc/host/tmio_mmc.h                   |   1 +
>  5 files changed, 303 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/mmc/host/renesas_sdhi_internal_dmac.c
> 
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 5755b69f2f72..81c81ed19735 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -575,10 +575,29 @@ config MMC_SDHI
>  	depends on SUPERH || ARM || ARM64
>  	depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
>  	select MMC_TMIO_CORE
> +	select MMC_SDHI_SYS_DMAC if (SUPERH || ARM)
> +	select MMC_SDHI_INTERNAL_DMAC if ARM64
>  	help
>  	  This provides support for the SDHI SD/SDIO controller found in
>  	  Renesas SuperH, ARM and ARM64 based SoCs
>  
> +config MMC_SDHI_SYS_DMAC
> +	tristate "DMA for SDHI SD/SDIO controllers using SYS-DMAC"
> +	depends on MMC_SDHI
> +	help
> +	  This provides DMA support for SDHI SD/SDIO controllers
> +	  using SYS-DMAC via DMA Engine. This supports the controllers
> +	  found in SuperH and Renesas ARM based SoCs.
> +
> +config MMC_SDHI_INTERNAL_DMAC
> +	tristate "DMA for SDHI SD/SDIO controllers using on-chip bus mastering"

0-day tells me that building fails on arm/allmodconfig due to
writeq not being defined. I believe this is because it only exists on
64bit systems. My proposed fix for v3 is:

	depends on 64BIT


> +	depends on ARM64 || COMPILE_TEST
> +	depends on MMC_SDHI
> +	help
> +	  This provides DMA support for SDHI SD/SDIO controllers
> +	  using on-chip bus mastering. This supports the controllers
> +	  found in arm64 based SoCs.
> +
>  config MMC_CB710
>  	tristate "ENE CB710 MMC/SD Interface support"
>  	depends on PCI

> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> index 4d4547116311..8c46766c000c 100644
> --- a/drivers/mmc/host/Makefile
> +++ b/drivers/mmc/host/Makefile

...

> +static void
> +renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host,
> +				    int addr, u64 val)
> +{
> +	writeq(val, host->ctl + addr);
> +}

...

Re: [PATCH mmc/next v2 2/4] mmc: tmio, renesas-sdhi: add complete to DMA ops

[Simon Horman]

On Sat, Jun 17, 2017 at 05:01:05PM +0200, Wolfram Sang wrote:
> On Fri, Jun 16, 2017 at 11:58:52AM +0200, Simon Horman wrote:
> > Add complete to DMA ops to allow DMAC implementation dependent
> > handling of DMA completion.
> > 
> > Also implement the operation for SDHI.
> > 
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> 
> Codewise, I am all fine with this patch. There is one naming, however:
> 
> > +	void (*complete)(struct tmio_mmc_host *host);
> 
> I'd rather call it 'dataend'. For internal DMAC, it is the same. But for
> SYS-DMAC there is difference between DATAEND and DMA_COMPLETE. This is
> exactly the reason we have commit 52ad9a8e854ca1 ("mmc: tmio: ensure end
> of DMA and SD access are in sync").
> 
> Basically, something like %s/complete/dataend/g would do it for me...

Sure, I will change this.

'compete' seemed like a nice name but I accept your reasoning above.

Re: [PATCH mmc/next v2 0/4] mmc: renesas_sdhi: add support for R-Car Gen3 SDHI DMAC

[Simon Horman]

On Sat, Jun 17, 2017 at 05:03:42PM +0200, Wolfram Sang wrote:
> > Based on mmc/next
> > 
> > Headline performance boost: 9.5MB/s -> 39.7MB/s
> 
> Did you test writing as well? For me, this fails on M3-W with CMD12
> timeouts. We had some changes in CMD12 handling recently, so it might be
> because of that. I'll check on Monday.
> 
> Visual code review follows...

No, for not particularly good reasons I only checked read.
I'll check write too.

Re: [PATCH mmc/next v2 3/4] mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC

[Simon Horman]

On Sat, Jun 17, 2017 at 10:55:50PM +0200, Simon Horman wrote:
> On Fri, Jun 16, 2017 at 11:58:53AM +0200, Simon Horman wrote:
> > Add a new variant of the SDHI driver to support R-Car Gen3 with DMA via
> > on-chip bus mastering.  Since the DMAC is in a part of the SDHI module it
> > is not suitable to be used via DMA Engine.
> > 
> > Clearing of DM_CM_INFO1 after DMA thanks to Dirk Behme
> > 
> > Cc: Dirk Behme <dirk.behme@de.bosch.com>
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > Signed-off-by: Ai Kyuse <ai.kyuse.uw@renesas.com>
> > ---
> > v2
> > * Enhanced help text and changelog
> > ---
> >  drivers/mmc/host/Kconfig                      |  19 ++
> >  drivers/mmc/host/Makefile                     |   8 +-
> >  drivers/mmc/host/renesas_sdhi_internal_dmac.c | 275 ++++++++++++++++++++++++++
> >  drivers/mmc/host/renesas_sdhi_sys_dmac.c      |   2 +-
> >  drivers/mmc/host/tmio_mmc.h                   |   1 +
> >  5 files changed, 303 insertions(+), 2 deletions(-)
> >  create mode 100644 drivers/mmc/host/renesas_sdhi_internal_dmac.c
> > 
> > diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> > index 5755b69f2f72..81c81ed19735 100644
> > --- a/drivers/mmc/host/Kconfig
> > +++ b/drivers/mmc/host/Kconfig
> > @@ -575,10 +575,29 @@ config MMC_SDHI
> >  	depends on SUPERH || ARM || ARM64
> >  	depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
> >  	select MMC_TMIO_CORE
> > +	select MMC_SDHI_SYS_DMAC if (SUPERH || ARM)
> > +	select MMC_SDHI_INTERNAL_DMAC if ARM64
> >  	help
> >  	  This provides support for the SDHI SD/SDIO controller found in
> >  	  Renesas SuperH, ARM and ARM64 based SoCs
> >  
> > +config MMC_SDHI_SYS_DMAC
> > +	tristate "DMA for SDHI SD/SDIO controllers using SYS-DMAC"
> > +	depends on MMC_SDHI
> > +	help
> > +	  This provides DMA support for SDHI SD/SDIO controllers
> > +	  using SYS-DMAC via DMA Engine. This supports the controllers
> > +	  found in SuperH and Renesas ARM based SoCs.
> > +
> > +config MMC_SDHI_INTERNAL_DMAC
> > +	tristate "DMA for SDHI SD/SDIO controllers using on-chip bus mastering"
> 
> 0-day tells me that building fails on arm/allmodconfig due to
> writeq not being defined. I believe this is because it only exists on
> 64bit systems. My proposed fix for v3 is:
> 
> 	depends on 64BIT

New proposal:

	#include <linux/io-64-nonatomic-hi-lo.h>

> > +	depends on ARM64 || COMPILE_TEST
> > +	depends on MMC_SDHI
> > +	help
> > +	  This provides DMA support for SDHI SD/SDIO controllers
> > +	  using on-chip bus mastering. This supports the controllers
> > +	  found in arm64 based SoCs.
> > +
> >  config MMC_CB710
> >  	tristate "ENE CB710 MMC/SD Interface support"
> >  	depends on PCI
> 
> > diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> > index 4d4547116311..8c46766c000c 100644
> > --- a/drivers/mmc/host/Makefile
> > +++ b/drivers/mmc/host/Makefile
> 
> ...
> 
> > +static void
> > +renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host,
> > +				    int addr, u64 val)
> > +{
> > +	writeq(val, host->ctl + addr);
> > +}
> 
> ...
> 

Re: [PATCH mmc/next v2 3/4] mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC

[Simon Horman]

On Sat, Jun 17, 2017 at 05:00:56PM +0200, Wolfram Sang wrote:
> On Fri, Jun 16, 2017 at 11:58:53AM +0200, Simon Horman wrote:
> > Add a new variant of the SDHI driver to support R-Car Gen3 with DMA via
> > on-chip bus mastering.  Since the DMAC is in a part of the SDHI module it
> > is not suitable to be used via DMA Engine.
> > 
> > Clearing of DM_CM_INFO1 after DMA thanks to Dirk Behme
> > 
> > Cc: Dirk Behme <dirk.behme@de.bosch.com>
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > Signed-off-by: Ai Kyuse <ai.kyuse.uw@renesas.com>
> 
> Your Sob is missing!

Yikes!

> 
> > + * - Since this SDHI DMAC register set has actual 32-bit and "bus_shift" is 2,
> > + *   this driver cannot use original sd_ctrl_{write,read}32 functions.
> 
> Easier to understand, I'd think, would be:
> 
> Since the SDHI DMAC register set has not 16 but 32-bit width, we need a
> custom accessor.

Thanks, updated.

> 
> > +	ret = dma_map_sg(&host->pdev->dev, sg, host->sg_len, dir);
> > +	if (ret < 0) {
> > +		dev_err(&host->pdev->dev, "%s: dma_map_sg failed\n", __func__);
> 
> __func__?

I have removed that message, it looks like an artifact of the development
process.

> 
> > +	/* start the DMAC */
> 
> Not very useful comment in my book, but no strong opinion.
> 
> > +	renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL,
> > +					    DTRAN_CTRL_DM_START);
> > +}
> > +	dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->sg_len, dir);
> > +
> > +	spin_unlock_irq(&host->lock);
> > +
> > +	spin_lock_irq(&host->lock);
> 
> Just keep the lock?

Yes, indeed.

> 
> Rest looks good so far...
>