From: oscardagrach <ryan@edited.us>
Cc: oscardagrach <ryan@edited.us>,
Jaehoon Chung <jh80.chung@samsung.com>,
Ulf Hansson <ulf.hansson@linaro.org>,
linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH] mmc: dw_mmc-k3: Fix DDR52 mode by setting required clock divisor
Date: Thu, 29 Mar 2018 13:24:22 -0500 [thread overview]
Message-ID: <20180329182423.21201-1-ryan@edited.us> (raw)
Signed-off-by: oscardagrach <ryan@edited.us>
---
drivers/mmc/host/dw_mmc-k3.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc-k3.c b/drivers/mmc/host/dw_mmc-k3.c
index 89cdb3d533bb..efc546cb4db8 100644
--- a/drivers/mmc/host/dw_mmc-k3.c
+++ b/drivers/mmc/host/dw_mmc-k3.c
@@ -194,8 +194,14 @@ static void dw_mci_hi6220_set_ios(struct dw_mci *host, struct mmc_ios *ios)
int ret;
unsigned int clock;
- clock = (ios->clock <= 25000000) ? 25000000 : ios->clock;
-
+ /* CLKDIV must be 1 for DDR52/8-bit mode */
+ if (ios->bus_width == MMC_BUS_WIDTH_8 &&
+ ios->timing == MMC_TIMING_MMC_DDR52) {
+ mci_writel(host, CLKDIV, 0x1);
+ clock = ios->clock;
+ } else {
+ clock = (ios->clock <= 25000000) ? 25000000 : ios->clock;
+ }
ret = clk_set_rate(host->biu_clk, clock);
if (ret)
dev_warn(host->dev, "failed to set rate %uHz\n", clock);
--
2.11.0
next reply other threads:[~2018-03-29 18:24 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-29 18:24 oscardagrach [this message]
2018-04-03 11:31 ` [PATCH] mmc: dw_mmc-k3: Fix DDR52 mode by setting required clock divisor Shawn Lin
[not found] ` <CAGoBSJq+tSpvFZsJLPffTaFBg5o2Nn2eeXXvHqt4Us_dd7==1w@mail.gmail.com>
2018-04-05 0:51 ` Shawn Lin
2018-04-05 2:08 ` zhangfei
2018-04-06 13:41 ` Ryan Grachek
2018-04-08 1:51 ` Shawn Lin
2018-04-08 8:23 ` 答复: " liwei (CM)
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