From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Ernest Zhang(WH)" Subject: [PATCH V2 1/2] mmc: sdhci: Fix O2 Host PLL and card detect issue Date: Tue, 18 Dec 2018 11:40:29 +0000 Message-ID: <20181218114003.10002-1-ernest.zhang@bayhubtech.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Adrian Hunter , Ulf Hansson , "linux-mmc@vger.kernel.org" , "linux-kernel@vger.kernel.org" Cc: "Andy Dai (WH)" , "Xiaoguang Yu (WH)" , "Shirley Her (SC)" , "Mike Li (WH)" , "Ernest Zhang(WH)" List-Id: linux-mmc@vger.kernel.org From: "Ernest Zhang" 1. O2 Host Controller PLL lock status is not in compliance with CLOCK_CONTROL register bit 1 2. O2 Host Controller card detect function only work when PLL is enabled and locked Signed-off-by: Ernest Zhang --- Change in V2: 1. Remove unused sdhci_ops function pointer 2. Change kind of timeout check, get the time first 3. Rename CARD PRESENT register bit16 and bit 18 macro Change in V1: N/A --- drivers/mmc/host/sdhci-pci-core.c | 9 +++ drivers/mmc/host/sdhci-pci-o2micro.c | 121 +++++++++++++++++++++++++++++++= +++- drivers/mmc/host/sdhci-pci.h | 1 + drivers/mmc/host/sdhci.h | 4 ++ 4 files changed, 132 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci= -core.c index 2a6eba74b94e..fc4f35653602 100644 --- a/drivers/mmc/host/sdhci-pci-core.c +++ b/drivers/mmc/host/sdhci-pci-core.c @@ -1257,6 +1257,14 @@ static int jmicron_resume(struct sdhci_pci_chip *chi= p) } #endif =20 +static const struct sdhci_ops sdhci_pci_o2_ops =3D { + .set_clock =3D sdhci_pci_o2_set_clock, + .enable_dma =3D sdhci_pci_enable_dma, + .set_bus_width =3D sdhci_set_bus_width, + .reset =3D sdhci_reset, + .set_uhs_signaling =3D sdhci_set_uhs_signaling, +}; + static const struct sdhci_pci_fixes sdhci_o2 =3D { .probe =3D sdhci_pci_o2_probe, .quirks =3D SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, @@ -1265,6 +1273,7 @@ static const struct sdhci_pci_fixes sdhci_o2 =3D { #ifdef CONFIG_PM_SLEEP .resume =3D sdhci_pci_o2_resume, #endif + .ops =3D &sdhci_pci_o2_ops, }; =20 static const struct sdhci_pci_fixes sdhci_jmicron =3D { diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-= pci-o2micro.c index cc3ffeffd7a2..506b93e5dcd8 100644 --- a/drivers/mmc/host/sdhci-pci-o2micro.c +++ b/drivers/mmc/host/sdhci-pci-o2micro.c @@ -60,6 +60,13 @@ #define O2_SD_VENDOR_SETTING2 0x1C8 #define O2_SD_HW_TUNING_DISABLE BIT(4) =20 +#define O2_PLL_WDT_CONTROL1 0x1CC +#define O2_PLL_FORCE_ACTIVE BIT(18) +#define O2_PLL_LOCK_STATUS BIT(14) +#define O2_PLL_SOFT_RESET BIT(12) + +#define O2_SD_DETECT_SETTING 0x324 + static void sdhci_o2_set_tuning_mode(struct sdhci_host *host) { u16 reg; @@ -283,6 +290,113 @@ static void sdhci_pci_o2_enable_msi(struct sdhci_pci_= chip *chip, host->irq =3D pci_irq_vector(chip->pdev, 0); } =20 +static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host) +{ + ktime_t timeout; + u32 scratch32; + + /* Wait max 50 ms */ + timeout =3D ktime_add_ms(ktime_get(), 50); + while (1) { + bool timedout =3D ktime_after(ktime_get(), timeout); + + scratch32 =3D sdhci_readl(host, SDHCI_PRESENT_STATE); + if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT + =3D=3D (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT) + break; + + if (timedout) { + pr_err("%s: Card Detect debounce never finished.\n", + mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return; + } + udelay(10); + } +} + +static void sdhci_o2_enable_internal_clock(struct sdhci_host *host) +{ + ktime_t timeout; + u16 scratch; + u32 scratch32; + + /* PLL software reset */ + scratch32 =3D sdhci_readl(host, O2_PLL_WDT_CONTROL1); + scratch32 |=3D O2_PLL_SOFT_RESET; + sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); + udelay(1); + scratch32 &=3D ~(O2_PLL_SOFT_RESET); + sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); + + /* PLL force active */ + scratch32 |=3D O2_PLL_FORCE_ACTIVE; + sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); + + /* Wait max 20 ms */ + timeout =3D ktime_add_ms(ktime_get(), 20); + while (1) { + bool timedout =3D ktime_after(ktime_get(), timeout); + + scratch =3D sdhci_readw(host, O2_PLL_WDT_CONTROL1); + if (scratch & O2_PLL_LOCK_STATUS) + break; + if (timedout) { + pr_err("%s: Internal clock never stabilised.\n", + mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + goto out; + } + udelay(10); + } + + /* Wait for card detect finish */ + udelay(1); + sdhci_o2_wait_card_detect_stable(host); + +out: + /* Cancel PLL force active */ + scratch32 =3D sdhci_readl(host, O2_PLL_WDT_CONTROL1); + scratch32 &=3D ~O2_PLL_FORCE_ACTIVE; + sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); +} + +static int sdhci_o2_get_cd(struct mmc_host *mmc) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + + sdhci_o2_enable_internal_clock(host); + + return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); +} + +static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk) +{ + /* Enable internal clock */ + clk |=3D SDHCI_CLOCK_INT_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + if (sdhci_o2_get_cd(host->mmc)) { + clk |=3D SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + } +} + +void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock) +{ + u16 clk; + + host->mmc->actual_clock =3D 0; + + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + + if (clock =3D=3D 0) + return; + + clk =3D sdhci_calc_clk(host, clock, &host->mmc->actual_clock); + sdhci_o2_enable_clk(host, clk); +} + int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot) { struct sdhci_pci_chip *chip; @@ -316,7 +430,11 @@ int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slo= t) host->flags |=3D SDHCI_SIGNALING_180; host->mmc->caps2 |=3D MMC_CAP2_NO_SD; host->mmc->caps2 |=3D MMC_CAP2_NO_SDIO; + pci_write_config_dword(chip->pdev, + O2_SD_DETECT_SETTING, 3); } + + slot->host->mmc_host_ops.get_cd =3D sdhci_o2_get_cd; } =20 host->mmc_host_ops.execute_tuning =3D sdhci_o2_execute_tuning; @@ -490,9 +608,6 @@ int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip) pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); break; case PCI_DEVICE_ID_O2_SEABIRD0: - if (chip->pdev->revision =3D=3D 0x01) - chip->quirks |=3D SDHCI_QUIRK_DELAY_AFTER_POWER; - /* fall through */ case PCI_DEVICE_ID_O2_SEABIRD1: /* UnLock WP */ ret =3D pci_read_config_byte(chip->pdev, diff --git a/drivers/mmc/host/sdhci-pci.h b/drivers/mmc/host/sdhci-pci.h index 2ef0bdca9197..e41a85f0b40a 100644 --- a/drivers/mmc/host/sdhci-pci.h +++ b/drivers/mmc/host/sdhci-pci.h @@ -184,6 +184,7 @@ int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip); #ifdef CONFIG_PM_SLEEP int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip); #endif +void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock); =20 extern const struct sdhci_pci_fixes sdhci_arasan; extern const struct sdhci_pci_fixes sdhci_snps; diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 6cc9a3c2ac66..924e03332cf7 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -73,6 +73,10 @@ #define SDHCI_SPACE_AVAILABLE 0x00000400 #define SDHCI_DATA_AVAILABLE 0x00000800 #define SDHCI_CARD_PRESENT 0x00010000 +#define SDHCI_CARD_PRES_SHIFT 16 +#define SDHCI_CD_STABLE 0x00020000 +#define SDHCI_CD_LVL 0x00040000 +#define SDHCI_CD_LVL_SHIFT 18 #define SDHCI_WRITE_PROTECT 0x00080000 #define SDHCI_DATA_LVL_MASK 0x00F00000 #define SDHCI_DATA_LVL_SHIFT 20 --=20 2.16.4