[PATCH 20/22] arm64: dts: imx8qxp: Remove i.MX7 compatible from UART

Krzysztof Kozlowski
2020-08-23T16:18:49Z

The UART on i.MX 8QXP has its own compatible described in bindings
and used in the driver (with its own quirks). Remove additional
fsl,imx7ulp-lpuart compatible to fix dtbs_check warnings like:

arch/arm64/boot/dts/freescale/imx8qxp-mek.dt.yaml: serial@5a060000:
compatible: ['fsl,imx8qxp-lpuart', 'fsl,imx7ulp-lpuart'] is too long
From schema: Documentation/devicetree/bindings/serial/fsl-lpuart.yaml

arch/arm64/boot/dts/freescale/imx8qxp-mek.dt.yaml: serial@5a060000:
compatible: Additional items are not allowed ('fsl,imx7ulp-lpuart' was unexpected)

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index e46faac1fe71..61bccb69f09e 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -257,7 +257,7 @@
};

adma_lpuart0: serial@5a060000 {
- compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+ compatible = "fsl,imx8qxp-lpuart";
reg = <0x5a060000 0x1000>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>,
@@ -268,7 +268,7 @@
};

adma_lpuart1: serial@5a070000 {
- compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+ compatible = "fsl,imx8qxp-lpuart";
reg = <0x5a070000 0x1000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>,
@@ -279,7 +279,7 @@
};

adma_lpuart2: serial@5a080000 {
- compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+ compatible = "fsl,imx8qxp-lpuart";
reg = <0x5a080000 0x1000>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>,
@@ -290,7 +290,7 @@
};

adma_lpuart3: serial@5a090000 {
- compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+ compatible = "fsl,imx8qxp-lpuart";
reg = <0x5a090000 0x1000>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>,
--
2.17.1