Re: [PATCH 2/2] mmc: renesas_sdhi: keep SCC clock active when tuning

Wolfram Sang
2020-09-01T13:47:42Z

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> not stalling the SCC. Anyhow, after this failute, the MMC core switches
> back to 300kHz and the SCC clock is off but for some reason SCC is still
> accessed. I will investigate why. The good news is that my new patch set
> fixes the hang as expected. The board will continue to boot so we
> probably want to have this series. However, I have the feeling that this
> SCC access which hangs the board might be a bug because of an unintended
> code path. I mean, this is also one reason why the bug triggers so
> rarely these days. We have been fixing a lot of things and the SCC is
> only accessed when it should be accessed. We will see. I also need to
> test other boards, too.

Some more good news: I can reproduce the issue now not only with
H3-ES2.0 but also with my M3-N.

Interesting news: The hang comes from a code path I would have not
expected. It is not because of accessing an SCC register, it is this
line from renesas_sdhi_set_clock() which causes the issue:

186 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);

I mean I can guess that the clock setting has something to do with the
SCC, but I can't see the direct connection with the documentation I
have.

I will stop that research here and will prepare now my series to leave
the SCC clock enabled as long as some tuning is in progress.

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