From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8134AC433EF for ; Thu, 9 Sep 2021 12:40:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5F61761100 for ; Thu, 9 Sep 2021 12:40:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344082AbhIIMls (ORCPT ); Thu, 9 Sep 2021 08:41:48 -0400 Received: from mail.kernel.org ([198.145.29.99]:46164 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348083AbhIIMhi (ORCPT ); Thu, 9 Sep 2021 08:37:38 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 7956C61BBF; Thu, 9 Sep 2021 11:54:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1631188467; bh=Jmw/wUq4Cw8gVxsFJPO7nTs4LAwlEVqSdbTxeDI4KAU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kXVomWzZ4pmw41S5OYrSQXAF/ZGO5SotkcBDP4cOdaMWO8lXEKJsOIUIxX8MCHKwv 97OuJsRBADYeON5ySbf90BvyRr+X3kOq2tVKGZYlG79DZUg0T4SkGR2eVnXGDOdbyk GpFmj5peSLTsiDmYRTZaXI/PIqPC/Xo58HUvAKZEG5O+IZC2FOY+ZSMMhCSLmHlCup E3/x+SnWe7Aj1MPtlcoxIFP6aSW9u1M7Lc/oCxgD+mDUAHkAeWWdH1voYkWK9pMeQp 1AyWMMaFzTRKhH+Na6J9E9zOaVDWIfEZWKpwW4wA6Ai7PVxUEOelzcmEukThiwP1bR bnRVfbDLSsX8A== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Manish Narani , Adrian Hunter , Ulf Hansson , Sasha Levin , linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org Subject: [PATCH AUTOSEL 5.10 146/176] mmc: sdhci-of-arasan: Modified SD default speed to 19MHz for ZynqMP Date: Thu, 9 Sep 2021 07:50:48 -0400 Message-Id: <20210909115118.146181-146-sashal@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210909115118.146181-1-sashal@kernel.org> References: <20210909115118.146181-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Manish Narani [ Upstream commit c0b4e411a9b09748466ee06d2ae6772effa64dfb ] SD standard speed timing was met only at 19MHz and not 25 MHz, that's why changing driver to 19MHz. The reason for this is when a level shifter is used on the board, timing was met for standard speed only at 19MHz. Since this level shifter is commonly required for high speed modes, the driver is modified to use standard speed of 19Mhz. Signed-off-by: Manish Narani Acked-by: Adrian Hunter Link: https://lore.kernel.org/r/1623753837-21035-2-git-send-email-manish.narani@xilinx.com Signed-off-by: Ulf Hansson Signed-off-by: Sasha Levin --- drivers/mmc/host/sdhci-of-arasan.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index 3b8d456e857d..0c5479a06e9e 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -159,6 +159,12 @@ struct sdhci_arasan_data { /* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the * internal clock even when the clock isn't stable */ #define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1) +/* + * Some of the Arasan variations might not have timing requirements + * met at 25MHz for Default Speed mode, those controllers work at + * 19MHz instead + */ +#define SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN BIT(2) }; struct sdhci_arasan_of_data { @@ -290,6 +296,16 @@ static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock) sdhci_arasan->is_phy_on = false; } + if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN) { + /* + * Some of the Arasan variations might not have timing + * requirements met at 25MHz for Default Speed mode, + * those controllers work at 19MHz instead. + */ + if (clock == DEFAULT_SPEED_MAX_DTR) + clock = (DEFAULT_SPEED_MAX_DTR * 19) / 25; + } + /* Set the Input and Output Clock Phase Delays */ if (clk_data->set_clk_delays) clk_data->set_clk_delays(host); @@ -1598,6 +1614,8 @@ static int sdhci_arasan_probe(struct platform_device *pdev) if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) { host->mmc_host_ops.execute_tuning = arasan_zynqmp_execute_tuning; + + sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN; } arasan_dt_parse_clk_phases(&pdev->dev, &sdhci_arasan->clk_data); -- 2.30.2