From: Piyush Malgujar <pmalgujar@marvell.com>
To: <linux-mmc@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<adrian.hunter@intel.com>, <ulf.hansson@linaro.org>,
<robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<yamada.masahiro@socionext.com>, <devicetree@vger.kernel.org>
Cc: <jannadurai@marvell.com>, <cchavva@marvell.com>,
Piyush Malgujar <pmalgujar@marvell.com>
Subject: [PATCH v3 6/6] mmc: sdhci-cadence: Add debug option for sdhci-cadence driver
Date: Mon, 27 Feb 2023 10:31:51 -0800 [thread overview]
Message-ID: <20230227183151.27912-7-pmalgujar@marvell.com> (raw)
In-Reply-To: <20230227183151.27912-1-pmalgujar@marvell.com>
From: Jayanthi Annadurai <jannadurai@marvell.com>
Use Kernel config CONFIG_MMC_DEBUG to support dumping PHY and host
controller register configuration for debug.
Signed-off-by: Jayanthi Annadurai <jannadurai@marvell.com>
Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com>
---
drivers/mmc/host/sdhci-cadence.c | 154 +++++++++++++++++++++++++++++++
1 file changed, 154 insertions(+)
diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
index badff2df70b904779c70775b02b40086780b118d..c448a100f32c8c44a0da7c71c2aa5d25ac5a4b44 100644
--- a/drivers/mmc/host/sdhci-cadence.c
+++ b/drivers/mmc/host/sdhci-cadence.c
@@ -115,6 +115,10 @@
#define SDHCI_CDNS_SD6_PHY_DLL_SLAVE_CLK_WR_DELAY GENMASK(15, 8)
#define SDHCI_CDNS_SD6_PHY_DLL_SLAVE_READ_DQS_DELAY GENMASK(7, 0)
+#define SDHCI_CDNS_SD6_PHY_DLL_OBS_REG0 0x201C
+#define SDHCI_CDNS_SD6_PHY_DLL_OBS_REG1 0x2020
+#define SDHCI_CDNS_SD6_PHY_DLL_OBS_REG2 0x2024
+
#define SDHCI_CDNS_SD6_PHY_CTRL 0x2080
#define SDHCI_CDNS_SD6_PHY_CTRL_PHONY_DQS_TIMING GENMASK(9, 4)
@@ -968,6 +972,154 @@ static void sdhci_cdns_sd6_calc_phy(struct sdhci_cdns_sd6_phy *phy)
}
}
+#ifdef CONFIG_MMC_DEBUG
+
+static
+void sdhci_cdns_sd6_phy_dump(struct sdhci_cdns_sd6_phy *phy,
+ struct sdhci_host *host)
+{
+ dev_dbg(mmc_dev(host->mmc), "PHY Timings\n");
+ dev_dbg(mmc_dev(host->mmc), "mode %d t_sdclk %d\n", phy->mode,
+ phy->t_sdclk);
+
+ dev_dbg(mmc_dev(host->mmc), "cp_clk_wr_delay %d\n",
+ phy->settings.cp_clk_wr_delay);
+ dev_dbg(mmc_dev(host->mmc), "cp_clk_wrdqs_delay %d\n",
+ phy->settings.cp_clk_wrdqs_delay);
+ dev_dbg(mmc_dev(host->mmc), "cp_data_select_oe_end %d\n",
+ phy->settings.cp_data_select_oe_end);
+ dev_dbg(mmc_dev(host->mmc), "cp_dll_bypass_mode %d\n",
+ phy->settings.cp_dll_bypass_mode);
+ dev_dbg(mmc_dev(host->mmc), "cp_dll_locked_mode %d\n",
+ phy->settings.cp_dll_locked_mode);
+ dev_dbg(mmc_dev(host->mmc), "cp_dll_start_point %d\n",
+ phy->settings.cp_dll_start_point);
+ dev_dbg(mmc_dev(host->mmc), "cp_io_mask_always_on %d\n",
+ phy->settings.cp_io_mask_always_on);
+ dev_dbg(mmc_dev(host->mmc), "cp_io_mask_end %d\n",
+ phy->settings.cp_io_mask_end);
+ dev_dbg(mmc_dev(host->mmc), "cp_io_mask_start %d\n",
+ phy->settings.cp_io_mask_start);
+ dev_dbg(mmc_dev(host->mmc), "cp_rd_del_sel %d\n",
+ phy->settings.cp_rd_del_sel);
+ dev_dbg(mmc_dev(host->mmc), "cp_read_dqs_cmd_delay %d\n",
+ phy->settings.cp_read_dqs_cmd_delay);
+ dev_dbg(mmc_dev(host->mmc), "cp_read_dqs_delay %d\n",
+ phy->settings.cp_read_dqs_delay);
+ dev_dbg(mmc_dev(host->mmc), "cp_sw_half_cycle_shift %d\n",
+ phy->settings.cp_sw_half_cycle_shift);
+ dev_dbg(mmc_dev(host->mmc), "cp_sync_method %d\n",
+ phy->settings.cp_sync_method);
+ dev_dbg(mmc_dev(host->mmc), "cp_use_ext_lpbk_dqs %d\n",
+ phy->settings.cp_use_ext_lpbk_dqs);
+ dev_dbg(mmc_dev(host->mmc), "cp_use_lpbk_dqs %d\n",
+ phy->settings.cp_use_lpbk_dqs);
+ dev_dbg(mmc_dev(host->mmc), "cp_use_phony_dqs %d\n",
+ phy->settings.cp_use_phony_dqs);
+ dev_dbg(mmc_dev(host->mmc), "cp_use_phony_dqs_cmd %d\n",
+ phy->settings.cp_use_phony_dqs_cmd);
+ dev_dbg(mmc_dev(host->mmc), "sdhc_extended_rd_mode %d\n",
+ phy->settings.sdhc_extended_rd_mode);
+ dev_dbg(mmc_dev(host->mmc), "sdhc_extended_wr_mode %d\n",
+ phy->settings.sdhc_extended_wr_mode);
+
+ dev_dbg(mmc_dev(host->mmc), "sdhc_hcsdclkadj %d\n",
+ phy->settings.sdhc_hcsdclkadj);
+ dev_dbg(mmc_dev(host->mmc), "sdhc_idelay_val %d\n",
+ phy->settings.sdhc_idelay_val);
+ dev_dbg(mmc_dev(host->mmc), "sdhc_rdcmd_en %d\n",
+ phy->settings.sdhc_rdcmd_en);
+ dev_dbg(mmc_dev(host->mmc), "sdhc_rddata_en %d\n",
+ phy->settings.sdhc_rddata_en);
+ dev_dbg(mmc_dev(host->mmc), "sdhc_rw_compensate %d\n",
+ phy->settings.sdhc_rw_compensate);
+ dev_dbg(mmc_dev(host->mmc), "sdhc_sdcfsh %d\n",
+ phy->settings.sdhc_sdcfsh);
+ dev_dbg(mmc_dev(host->mmc), "sdhc_sdcfsl %d\n",
+ phy->settings.sdhc_sdcfsl);
+ dev_dbg(mmc_dev(host->mmc), "sdhc_wrcmd0_dly %d %d\n",
+ phy->settings.sdhc_wrcmd0_dly,
+ phy->settings.sdhc_wrcmd0_sdclk_dly);
+ dev_dbg(mmc_dev(host->mmc), "sdhc_wrcmd1_dly %d %d\n",
+ phy->settings.sdhc_wrcmd1_dly,
+ phy->settings.sdhc_wrcmd1_sdclk_dly);
+ dev_dbg(mmc_dev(host->mmc), "sdhc_wrdata0_dly %d %d\n",
+ phy->settings.sdhc_wrdata0_dly,
+ phy->settings.sdhc_wrdata0_sdclk_dly);
+
+ dev_dbg(mmc_dev(host->mmc), "sdhc_wrdata1_dly %d %d\n",
+ phy->settings.sdhc_wrdata1_dly,
+ phy->settings.sdhc_wrdata1_sdclk_dly);
+ dev_dbg(mmc_dev(host->mmc), "hs200_tune_val %d\n",
+ phy->settings.hs200_tune_val);
+}
+
+static
+void sdhci_cdns_sd6_dump(struct sdhci_cdns_priv *priv, struct sdhci_host *host)
+{
+ struct sdhci_cdns_sd6_phy *phy = priv->phy;
+ int id;
+
+ sdhci_cdns_sd6_phy_dump(phy);
+
+ dev_dbg(mmc_dev(host->mmc), "Host controller Register Dump\n");
+ for (id = 0; id < 14; id++) {
+ dev_dbg(mmc_dev(host->mmc), "HRS%d 0x%x\n", id,
+ readl(priv->hrs_addr + (id * 4)));
+ }
+
+ id = 29;
+ dev_dbg(mmc_dev(host->mmc), "HRS%d 0x%x\n", id,
+ readl(priv->hrs_addr + (id * 4)));
+ id = 30;
+ dev_dbg(mmc_dev(host->mmc), "HRS%d 0x%x\n", id,
+ readl(priv->hrs_addr + (id * 4)));
+
+ for (id = 0; id < 27; id++) {
+ dev_dbg(mmc_dev(host->mmc), "SRS%d 0x%x\n", id,
+ readl(priv->hrs_addr + 0x200 + (id * 4)));
+ }
+
+ dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DQS_TIMING 0x%x\n",
+ sdhci_cdns_sd6_read_phy_reg(priv,
+ SDHCI_CDNS_SD6_PHY_DQS_TIMING));
+ dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_GATE_LPBK 0x%x\n",
+ sdhci_cdns_sd6_read_phy_reg(priv,
+ SDHCI_CDNS_SD6_PHY_GATE_LPBK));
+ dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_MASTER 0x%x\n",
+ sdhci_cdns_sd6_read_phy_reg(priv,
+ SDHCI_CDNS_SD6_PHY_DLL_MASTER));
+ dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_SLAVE 0x%x\n",
+ sdhci_cdns_sd6_read_phy_reg(priv,
+ SDHCI_CDNS_SD6_PHY_DLL_SLAVE));
+ dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_CTRL 0x%x\n",
+ sdhci_cdns_sd6_read_phy_reg(priv, SDHCI_CDNS_SD6_PHY_CTRL));
+ dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_GPIO_CTRL0 0x%x\n",
+ sdhci_cdns_sd6_read_phy_reg(priv,
+ SDHCI_CDNS_SD6_PHY_GPIO_CTRL0));
+ dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DQ_TIMING 0x%x\n",
+ sdhci_cdns_sd6_read_phy_reg(priv,
+ SDHCI_CDNS_SD6_PHY_DQ_TIMING));
+ dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_OBS_REG0 0x%x\n",
+ sdhci_cdns_sd6_read_phy_reg(priv,
+ SDHCI_CDNS_SD6_PHY_DLL_OBS_REG0));
+ dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_OBS_REG1 0x%x\n",
+ sdhci_cdns_sd6_read_phy_reg(priv,
+ SDHCI_CDNS_SD6_PHY_DLL_OBS_REG1));
+ dev_dbg(mmc_dev(host->mmc), "SDHCI_CDNS_SD6_PHY_DLL_OBS_REG2 0x%x\n",
+ sdhci_cdns_sd6_read_phy_reg(priv,
+ SDHCI_CDNS_SD6_PHY_DLL_OBS_REG2));
+}
+
+#else
+
+static inline void sdhci_cdns_sd6_dump(struct sdhci_cdns_priv *priv,
+ struct sdhci_host *host)
+{
+}
+
+#endif
+
static
int sdhci_cdns_sd6_get_delay_params(struct device *dev,
struct sdhci_cdns_priv *priv)
@@ -1319,6 +1471,8 @@ static void sdhci_cdns_sd6_set_clock(struct sdhci_host *host,
pr_debug("%s: phy init failed\n", __func__);
sdhci_set_clock(host, clock);
+
+ sdhci_cdns_sd6_dump(priv, host);
}
static int sdhci_cdns_sd4_phy_probe(struct platform_device *pdev,
--
2.17.1
next prev parent reply other threads:[~2023-02-27 18:33 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-27 18:31 [PATCH v3 0/6] mmc: sdhci-cadence: SD6 controller support Piyush Malgujar
2023-02-27 18:31 ` [PATCH v3 1/6] mmc: sdhci-cadence: Rename functions to SD4 specific Piyush Malgujar
2023-02-27 18:31 ` [PATCH v3 2/6] mmc: sdhci-cadence: Restructure the code Piyush Malgujar
2023-03-03 8:36 ` Adrian Hunter
2023-03-24 15:19 ` Piyush Malgujar
2023-02-27 18:31 ` [PATCH v3 3/6] mmc: sdhci-cadence: SD6 controller support Piyush Malgujar
2023-03-03 8:48 ` Adrian Hunter
2023-02-27 18:31 ` [PATCH v3 4/6] mmc: sdhci-cadence: enable MMC_SDHCI_IO_ACCESSORS Piyush Malgujar
2023-02-27 18:31 ` [PATCH v3 5/6] dt-bindings: mmc: sdhci-cadence: SD6 support Piyush Malgujar
2023-02-28 10:53 ` Krzysztof Kozlowski
2023-03-24 15:02 ` Piyush Malgujar
2023-02-28 15:46 ` Rob Herring
2023-03-24 15:13 ` Piyush Malgujar
2023-02-27 18:31 ` Piyush Malgujar [this message]
2023-03-03 8:36 ` [PATCH v3 6/6] mmc: sdhci-cadence: Add debug option for sdhci-cadence driver Adrian Hunter
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230227183151.27912-7-pmalgujar@marvell.com \
--to=pmalgujar@marvell.com \
--cc=adrian.hunter@intel.com \
--cc=cchavva@marvell.com \
--cc=devicetree@vger.kernel.org \
--cc=jannadurai@marvell.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mmc@vger.kernel.org \
--cc=robh+dt@kernel.org \
--cc=ulf.hansson@linaro.org \
--cc=yamada.masahiro@socionext.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox