From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6ACB337BA3 for ; Fri, 8 May 2026 17:23:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.178 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778261014; cv=none; b=lzii5SfbmXx5UgyU2X/9gaUdH0If+fXmB8bPW2gY4zS52mxkHTuGU/JQ6rW6/mfdDfCv4JyTErh3p+qfW+TDRVxqpKw9dqoxfAiHecSncOjzj33CVt7bFclYANAxaFxL0zSN70Xw/5pkvMkGjOXk2oj85/pvbfY7Np1rjm+TN5o= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778261014; c=relaxed/simple; bh=/N9shEYpuzBmz3d2S1zCxWvYnr9A/2N8v8wLaRysY8I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QAtMVnVW4ORvuZQtJl0t3kvOqpi5isQK1qtv3Y3Tfk0X+k5gbe2QLvtT/SK8U190rJPJnF9nBiPzOc9XiIPhxWRdHKF9fj7wDGdVrFNRN5caNEkqzGXOPjg/QWE46jtALIm0OhDFevON0v+WGRLmy01uy9R+ZJFhtQ8Rbp9lGKA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=hBIfmC3N; arc=none smtp.client-ip=209.85.214.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hBIfmC3N" Received: by mail-pl1-f178.google.com with SMTP id d9443c01a7336-2b9705613ddso15139475ad.1 for ; Fri, 08 May 2026 10:23:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1778261005; x=1778865805; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=uFMAJRct5+Ew9bo4NrSDVyJ5C+wmVXcn6c9x8tk7NTk=; b=hBIfmC3N3GqMnKrKapnFDD3xP71jfHJCzcmz/6uz0fFwzDQOffeNRl6oBdAhjkN+Pm swezXw9XXsu6y8urYHK9oOtMag71+0nsgevLECp+L67TEBO8sp+XXdAR70756mzXWn+p PPa/kfzJN2u5MLU7sqgCTubLUENhFNfWy3S4e4zSxtc3roDAJno7QNvMsO9JtCpJcPmY r6ywjOAHwM2dAYu3qIv66BeYdNVIHuKvTJCDIpMMpJYuZxOnWzhWNx/NVNMyNwd4RWmP N3pnCB6o+Nh2MX76FkVbEfM+nQHu+YHY67okx2aj9gCxSs79A76dLBYeOG1V2J+6WOwI C/vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778261005; x=1778865805; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=uFMAJRct5+Ew9bo4NrSDVyJ5C+wmVXcn6c9x8tk7NTk=; b=mMsvBRsYOT6fQmyBmNx9qi1Sw/ZpdLSQyKaw2bc3kSswYslQxvpD1ATv/ERj/p8V3F 0UyXk/dD9EfKnYRyyU1k923RdhgQBToXxhBmoV/BKbqqg1tHTj+XAvSgZ2TnwH/T0/HE zZJWP7/x/ZaRUvxX//8xXX458c/fKKUCGSVHuM0UfY/IEGFjB9GYecVNXgdjCSBufSAq NRZ4Q5zwWTp3+NG7o+Skx92Ce3cHPgISUrtZmsksOjwA1m0sfmqgDOgsNXL2/+2t1tm4 03ESdCGk0m399+XS/uSSAbJ6561QjeM6lZUq4GdHui19oMT0tgw1S4OZ0pfRhDIvxnGn yq+w== X-Gm-Message-State: AOJu0YyepUgRdrHpKIUifY6KowVPmhlOXhGqcFDKL8qTr1voyJkj80yN cmUXTxrwF5HgA+ytvhUQq2jHWRTaZ80lfLYF0LZRTdmge5ZMCPCRexfPU7/0Qg== X-Gm-Gg: Acq92OENdj0iupXefucGEZHNs8gvOATiETMz1kxCpu4XCpy27jETeq2WqY/Is1kg0md R7WzZnfbsrJem3QiBYjvkg72YD+3FJT7T9Ppy0o2WXnTRTh3jKRb5Tg9ctfTAYgaMJxmqwbSfnu 5X6baaRubwzJ/Ji5uzD1kkJqS2lPj72WlXMSYwT8ovHpxT5TEphds26QZI3QteNs5UTkR9oL0tb APw5r274txpBKu58t3D5Xn1eT9HPP7M2W+ex/Aw3x1fGU0C9lvOYqwP8lj8iqBGtVx07Wm8soTJ PEdmG0wovE98O72EjtQtNTeJIbohWj+i4LYK4xNMMQo//8u2CpWh/NfeGzFT+Pgk6antggDgKyu euvoqQ3QOdvS3+o2P1iVHzq6cqkI79BJjjhDdVDg7fokm0e80o3apqR0Q9wlqG9YxD7vLEF3JCH 2lFnkVC7dm87BFXkxVpkJ8Bba9YqKuWWVkJ5c/yiJ9E4rW X-Received: by 2002:a17:903:1ab0:b0:2b2:4ffc:a7c4 with SMTP id d9443c01a7336-2ba798c0a22mr119825725ad.24.1778261004803; Fri, 08 May 2026 10:23:24 -0700 (PDT) Received: from Black-Pearl.localdomain ([60.243.224.75]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-2baf1e35487sm24907985ad.46.2026.05.08.10.23.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 May 2026 10:23:24 -0700 (PDT) From: Charan Pedumuru Date: Fri, 08 May 2026 17:23:07 +0000 Subject: [PATCH v3 2/2] dt-bindings: mmc: st,sdhci: convert to DT schema Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260508-st-mmc-v3-2-81c329ed28e8@gmail.com> References: <20260508-st-mmc-v3-0-81c329ed28e8@gmail.com> In-Reply-To: <20260508-st-mmc-v3-0-81c329ed28e8@gmail.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , Patrice Chotard Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Charan Pedumuru X-Mailer: b4 0.15.2 Convert STMicroelectronics sdhci-st MMC/SD controller binding to DT schema. Changes during conversion: - In the legacy text binding, 'icn' was optional. Keep the clock list flexible to preserve compatibility, although all existing in-tree DTS files already provide both clocks. - Document the optional "top-mmc-delay" register region and corresponding reg-name in the YAML binding, as existing in-tree DTS files already use both "mmc" and "top-mmc-delay" entries. Signed-off-by: Charan Pedumuru --- Documentation/devicetree/bindings/mmc/sdhci-st.txt | 110 --------------------- .../devicetree/bindings/mmc/st,sdhci.yaml | 91 +++++++++++++++++ 2 files changed, 91 insertions(+), 110 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-st.txt b/Documentation/devicetree/bindings/mmc/sdhci-st.txt deleted file mode 100644 index ccf82b4ee838..000000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci-st.txt +++ /dev/null @@ -1,110 +0,0 @@ -* STMicroelectronics sdhci-st MMC/SD controller - -This file documents the differences between the core properties in -Documentation/devicetree/bindings/mmc/mmc.txt and the properties -used by the sdhci-st driver. - -Required properties: -- compatible: Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407" - to set the internal glue logic used for configuring the MMC - subsystem (mmcss) inside the FlashSS (available in STiH407 SoC - family). - -- clock-names: Should be "mmc" and "icn". (NB: The latter is not compulsory) - See: Documentation/devicetree/bindings/resource-names.txt -- clocks: Phandle to the clock. - See: Documentation/devicetree/bindings/clock/clock-bindings.txt - -- interrupts: One mmc interrupt should be described here. -- interrupt-names: Should be "mmcirq". - -- pinctrl-names: A pinctrl state names "default" must be defined. -- pinctrl-0: Phandle referencing pin configuration of the sd/emmc controller. - See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -- reg: This must provide the host controller base address and it can also - contain the FlashSS Top register for TX/RX delay used by the driver - to configure DLL inside the flashSS, if so reg-names must also be - specified. - -Optional properties: -- reg-names: Should be "mmc" and "top-mmc-delay". "top-mmc-delay" is optional - for eMMC on stih407 family silicon to configure DLL inside FlashSS. - -- non-removable: Non-removable slot. Also used for configuring mmcss in STiH407 SoC - family. - See: Documentation/devicetree/bindings/mmc/mmc.txt. - -- bus-width: Number of data lines. - See: Documentation/devicetree/bindings/mmc/mmc.txt. - -- max-frequency: Can be 200MHz, 100MHz or 50MHz (default) and used for - configuring the CCONFIG3 in the mmcss. - See: Documentation/devicetree/bindings/mmc/mmc.txt. - -- resets: Phandle and reset specifier pair to softreset line of HC IP. - See: Documentation/devicetree/bindings/reset/reset.txt - -- vqmmc-supply: Phandle to the regulator dt node, mentioned as the vcc/vdd - supply in eMMC/SD specs. - -- sd-uhs-sdr50: To enable the SDR50 in the mmcss. - See: Documentation/devicetree/bindings/mmc/mmc.txt. - -- sd-uhs-sdr104: To enable the SDR104 in the mmcss. - See: Documentation/devicetree/bindings/mmc/mmc.txt. - -- sd-uhs-ddr50: To enable the DDR50 in the mmcss. - See: Documentation/devicetree/bindings/mmc/mmc.txt. - -Example: - -/* Example stih416e eMMC configuration */ - -mmc0: sdhci@fe81e000 { - compatible = "st,sdhci"; - reg = <0xfe81e000 0x1000>; - interrupts = ; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0>; - clock-names = "mmc"; - clocks = <&clk_s_a1_ls 1>; - bus-width = <8> - -/* Example SD stih407 family configuration */ - -mmc1: sdhci@9080000 { - compatible = "st,sdhci-stih407", "st,sdhci"; - reg = <0x09080000 0x7ff>; - reg-names = "mmc"; - interrupts = ; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd1>; - clock-names = "mmc"; - clocks = <&clk_s_c0_flexgen CLK_MMC_1>; - resets = <&softreset STIH407_MMC1_SOFTRESET>; - bus-width = <4>; -}; - -/* Example eMMC stih407 family configuration */ - -mmc0: sdhci@9060000 { - compatible = "st,sdhci-stih407", "st,sdhci"; - reg = <0x09060000 0x7ff>, <0x9061008 0x20>; - reg-names = "mmc", "top-mmc-delay"; - interrupts = ; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0>; - clock-names = "mmc"; - clocks = <&clk_s_c0_flexgen CLK_MMC_0>; - vqmmc-supply = <&vmmc_reg>; - max-frequency = <200000000>; - bus-width = <8>; - non-removable; - sd-uhs-sdr50; - sd-uhs-sdr104; - sd-uhs-ddr50; -}; diff --git a/Documentation/devicetree/bindings/mmc/st,sdhci.yaml b/Documentation/devicetree/bindings/mmc/st,sdhci.yaml new file mode 100644 index 000000000000..10e0e1ee6d5c --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/st,sdhci.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/st,sdhci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics SDHCI-ST MMC/SD Controller + +description: + The STMicroelectronics SDHCI-ST MMC/SD host controller, which is + compliant with the SD Host Controller Interface (SDHCI) specification and + is used to interface with MMC, SD and SDIO cards. The ST SDHCI controller + extends the standard SDHCI capabilities with platform-specific + configurations such as additional register regions,clock inputs, and delay + control mechanisms required for signal timing adjustments which are + necessary to support high-speed modes and ensure reliable data transfer + across different ST SoCs. + +allOf: + - $ref: mmc-controller.yaml# + +maintainers: + - Peter Griffin + +properties: + compatible: + oneOf: + - const: st,sdhci + - items: + - const: st,sdhci-stih407 + - const: st,sdhci + + reg: + minItems: 1 + items: + - description: MMC controller registers + - description: MMC delay/auxiliary registers + + reg-names: + items: + - const: mmc + - const: top-mmc-delay + + clocks: + minItems: 1 + items: + - description: Clock for the MMC controller + - description: Interconnect (ICN) clock + + clock-names: + items: + - const: mmc + - const: icn + + interrupts: + maxItems: 1 + + interrupt-names: + const: mmcirq + + resets: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + mmc@9060000 { + compatible = "st,sdhci-stih407", "st,sdhci"; + reg = <0x09060000 0x7ff>, <0x9061008 0x20>; + reg-names = "mmc", "top-mmc-delay"; + interrupts = ; + interrupt-names = "mmcirq"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0>; + clock-names = "mmc", "icn"; + clocks = <&clk_s_c0_flexgen CLK_MMC_0>, + <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; + bus-width = <8>; + }; +... -- 2.54.0