Re: [PATCH v3 1/8] dt-bindings: mmc: add Cadence SD6HC binding

[Krzysztof Kozlowski <krzk@kernel.org>]

On Fri, Jul 24, 2026 at 07:50:00AM -0700, Tanmay Kathpalia wrote:
> +description:
> +  Cadence SD6HC is a sixth-generation SD/SDIO/eMMC host controller with an
> +  interface to a Cadence Combo PHY. The controller has separate card interface
> +  and bus interface clock domains.
> +
> +properties:
> +  compatible:
> +    items:
> +      - const: altr,agilex5-sd6hc
> +      - const: cdns,sd6hc
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: card interface unit (CIU / SDMCLK) clock
> +      - description: bus interface unit (BIU) clock
> +
> +  clock-names:
> +    items:
> +      - const: ciu
> +      - const: biu
> +
> +  resets:
> +    minItems: 1

Drop

> +    maxItems: 3
> +
> +  reset-names:
> +    minItems: 1
> +    maxItems: 3

Drop both and list items. And then drop that "if:then:" block.

Case of 1 item is simply impossible.

> +
> +  iommus:
> +    maxItems: 1
> +
> +  dma-coherent: true
> +
> +  cdns,iocell-input-delay-ps:
> +    description:
> +      Input delay across the IO cells, used for SD6HC PHY timing calculations.
> +    minimum: 0
> +    maximum: 20000
> +
> +  cdns,iocell-output-delay-ps:
> +    description:
> +      Output delay across the IO cells, used for SD6HC PHY timing calculations.
> +    minimum: 0
> +    maximum: 20000
> +
> +  cdns,delay-element-ps:
> +    description:
> +      DLL delay element size, used for SD6HC PHY timing calculations.
> +    minimum: 1
> +    maximum: 1000
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +  - clock-names

resets and reset-names should be required

> +
> +allOf:
> +  - $ref: sdhci-common.yaml#
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: altr,agilex5-sd6hc

Best regards,
Krzysztof