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Mon, 3 Aug 2026 15:48:27 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1785764910; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding; bh=/+DsmGd9kahA+v8FP72hTxMpgTQQBsFpc1AqdkO89sI=; b=aXGt/PO2vTKkgolUymTtqTlulAQooiQkUVPbnRi/zc3yGRER07GWsLZSbMjmlFlZyxZA/o jDAq5hr9l5OKeNvOPfyiKu12IdcAUvVnjmPul/S1I2KgyBVX+AtNqr04K3ksME7NMaYwcN 5pKWLAeb1YDlJxmeOn+Hpvg/hRrNux8IRW+AjRFsftThRz8r/B6iTfIpSXize52X4m89aE nxKJ/sbIM030bCdfk3HR/JbN5lCSmLTx//2Bs4COej9rRLDwFWeC1C3ZeeyzIIGxAKFqxQ d9sN6EloZOsUK80HWGQ7RrH8s5/2D2R868mnHmP2jlhgvIs+ICQgs/1rxGQ+hA== From: "Diogo Ivo (Schneider Electric)" Subject: [PATCH v2 0/4] mmc: sdhci_am654: Fix DDR50 mode for cards without tuning support Date: Mon, 03 Aug 2026 15:47:30 +0200 Message-Id: <20260803-am654-sdhci-v2-0-a5ee5be86133@bootlin.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; 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a=openpgp; fpr=E66B7E68D62D74F357BC076506BE7C5B565EC945 X-Last-TLS-Session-Version: TLSv1.3 DDR50 mode is not required to support the tuning command CMD19 by the eMMC/SD specification, meaning that calibration may fail on cards that do not implement it. This series fixes four issues discovered when using such cards: - Patch 1 moves the tuning_loop counter from a persistent struct field to a local variable, preventing failed tuning attempts from depleting the retry budget across calls. - Patch 2 ensures the command/data line reset is always performed after tuning, even on failure, preventing stale data in the controller buffer. - Patch 3 clears the ITAPDLY enable and delay values on tuning failure so that leftover calibration values do not interfere with subsequent I/O. - Patch 4 falls back to the DT-provided itap delay value for DDR50 when tuning fails in this mode, making a best-effort attempt at a known-good delay being programmed. Together these changes make DDR50 functional on TI J721E SoCs with cards that lack CMD19 tuning support. This second version addresses all comments from Sashiko, which I found to be correct. Signed-off-by: Diogo Ivo (Schneider Electric) --- Changes in v2: - Add new patch moving tuning_loop to a local variable (Patch 1) - Clear ITAPDLY array values alongside HW registers on tuning failure (Patch 3) - Save DT-provided itap delay values for DDR50 in dedicated variables to preserve them across tuning cycles (Patch 4) - Link to v1: https://patch.msgid.link/20260729-am654-sdhci-v1-0-7568108e4b9a@bootlin.com --- Diogo Ivo (Schneider Electric) (4): mmc: sdhci_am654: Move tuning_loop to local variable mmc: sdhci_am654: Reset command and data lines on failed tuning mmc: sdhci_am654: Clear ITAPDLY on tuning failure mmc: sdhci_am654: Fallback to DT-provided itap delay on DDR50 tuning failure drivers/mmc/host/sdhci_am654.c | 42 +++++++++++++++++++++++++++--------------- 1 file changed, 27 insertions(+), 15 deletions(-) --- base-commit: f932188d6b0b684ee8555c8ecf1cac3567c4b106 change-id: 20260728-am654-sdhci-85094d458bae Best regards, -- Diogo Ivo