[PATCH] mmc: sunplus: initialise rd_crc_dly=1 for DDR modes

[Andrew Gaylard <ag@ffroot.co.za>]

After spmmc_controller_init() resets the controller, all timing
fields are zero.  The hs_en path initialises the write timing
delays (wr_cmd_dly, wr_dat_dly) but leaves the read side at zero.

In DDR52 mode, rd_crc_dly=0 causes the first write to fail with
CRC_TOKEN_CHECK_ERROR, triggering the auto-tuning retry loop and
causing a multi-second delay on the first cold-boot write.

Set rd_crc_dly=1 when enabling DDR mode to avoid this.

Tested on a LTPP3G2, booting via eMMC in DDR52 mode,
on linux-next-20260915.

Signed-off-by: Andrew Gaylard <ag@ffroot.co.za>
---
 drivers/mmc/host/sunplus-mmc.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/mmc/host/sunplus-mmc.c b/drivers/mmc/host/sunplus-mmc.c
index 63279760239c..e947c84eef94 100644
--- a/drivers/mmc/host/sunplus-mmc.c
+++ b/drivers/mmc/host/sunplus-mmc.c
@@ -294,6 +294,11 @@ static void spmmc_set_bus_timing(struct spmmc_host *host, unsigned int timing)
 		value = readl(host->base + SPMMC_SD_CONFIG0_REG);
 		value |= SPMMC_SD_DDR_MODE;
 		writel(value, host->base + SPMMC_SD_CONFIG0_REG);
+		/* DDR mode needs rd_crc_dly=1 */
+		value = readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG);
+		value &= ~SPMMC_SD_READ_CRC_DELAY;
+		value |= FIELD_PREP(SPMMC_SD_READ_CRC_DELAY, 1);
+		writel(value, host->base + SPMMC_SD_TIMING_CONFIG0_REG);
 	} else {
 		value = readl(host->base + SPMMC_SD_CONFIG0_REG);
 		value &= ~SPMMC_SD_DDR_MODE;
-- 
2.53.0