From: Adrian Hunter <adrian.hunter@intel.com>
To: Robert Marko <robert.marko@sartura.hr>, <ulfh@kernel.org>,
<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
<nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
<claudiu.beznea@tuxon.dev>, <aubin.constans@microchip.com>,
<ehristev@kernel.org>, <linux-mmc@vger.kernel.org>,
<devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Cc: <luka.perkov@sartura.hr>
Subject: Re: [PATCH v2 3/6] mmc: sdhci-of-at91: add LAN969x support
Date: Wed, 9 Sep 2026 13:36:14 +0300 [thread overview]
Message-ID: <2d7a6e8b-029a-4b9e-b7d4-8b7e96ea6aa0@intel.com> (raw)
In-Reply-To: <20260907132617.1198548-4-robert.marko@sartura.hr>
On 07/09/2026 16:25, Robert Marko wrote:
> LAN969x uses the same internally generated base clock layout as SAM9X60,
> but its SDMMC controller stops responding when runtime PM gates its clocks.
> Software resets then fail to complete and the internal SDHCI clock never
> stabilises, causing subsequent I/O requests to time out.
Is this a known issue of the SoC? Is there perhaps a hardware reset
for the controller that would bring it back to life?
Does that mean unbind and rebind of the device from the driver
also does not work?
>
> Add LAN969x-specific SoC data using the SAM9X60 clock layout and select the
> option to leave its clocks enabled across runtime suspend.
>
> Signed-off-by: Robert Marko <robert.marko@sartura.hr>
>
> drivers/mmc/host/sdhci-of-at91.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-of-at91.c b/drivers/mmc/host/sdhci-of-at91.c
> index b7e2a89da348..e7affca8da25 100644
> --- a/drivers/mmc/host/sdhci-of-at91.c
> +++ b/drivers/mmc/host/sdhci-of-at91.c
> @@ -158,9 +158,17 @@ static const struct sdhci_at91_soc_data soc_data_sam9x60 = {
> .divider_for_baseclk = 2,
> };
>
> +static const struct sdhci_at91_soc_data soc_data_lan969x = {
> + .pdata = &sdhci_sama5d2_pdata,
> + .baseclk_is_generated_internally = true,
Should be a comment here explaining the issue that needs
keep_clks_on = true
> + .keep_clks_on = true,
> + .divider_for_baseclk = 2,
> +};
> +
> static const struct of_device_id sdhci_at91_dt_match[] = {
> { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 },
> { .compatible = "microchip,sam9x60-sdhci", .data = &soc_data_sam9x60 },
> + { .compatible = "microchip,lan9691-sdhci", .data = &soc_data_lan969x },
> {}
> };
> MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match);
next prev parent reply other threads:[~2026-09-09 10:42 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-07 13:25 [PATCH v2 0/6] mmc: sdhci-of-at91: add LAN969x support Robert Marko
2026-09-07 13:25 ` [PATCH v2 1/6] dt-bindings: mmc: atmel,sama5d2-sdhci: add LAN969x compatible Robert Marko
2026-09-07 13:25 ` [PATCH v2 2/6] mmc: sdhci-of-at91: add option to keep clocks enabled Robert Marko
2026-09-09 10:31 ` Adrian Hunter
2026-09-14 13:46 ` Aubin Constans
2026-09-07 13:25 ` [PATCH v2 3/6] mmc: sdhci-of-at91: add LAN969x support Robert Marko
2026-09-09 10:36 ` Adrian Hunter [this message]
2026-09-07 13:25 ` [PATCH v2 4/6] arm64: dts: microchip: lan969x: add SDMMC nodes Robert Marko
2026-09-07 13:58 ` Aubin Constans
2026-09-07 13:25 ` [PATCH v2 5/6] arm64: dts: microchip: ev23x71a: enable QSPI Robert Marko
2026-09-07 13:25 ` [PATCH v2 6/6] arm64: dts: microchip: ev23x71a: enable eMMC Robert Marko
2026-09-07 14:18 ` Aubin Constans
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