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Tue, 24 Sep 2024 12:11:04 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48OCB22u011774 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 24 Sep 2024 12:11:02 GMT Received: from [10.151.37.100] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 24 Sep 2024 05:10:55 -0700 Message-ID: <30fdcb3e-a7ff-4764-bed5-39494c3e3326@quicinc.com> Date: Tue, 24 Sep 2024 17:40:52 +0530 Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Sricharan Ramabadhran Subject: Re: [PATCH 1/8] dt-bindings: clock: Add Qualcomm IPQ5424 GCC To: Krzysztof Kozlowski , , , , , , , , , , , , , , , , , , , , , CC: References: <20240913121250.2995351-1-quic_srichara@quicinc.com> <20240913121250.2995351-2-quic_srichara@quicinc.com> <4cd3d3f8-7d73-4171-bb35-aba975cdc11a@kernel.org> <9f2ccf3d-fa71-4784-b6d2-2b12ed50bdd2@quicinc.com> <91392141-af8b-4161-8e76-6f461aaba42a@kernel.org> Content-Language: en-US In-Reply-To: <91392141-af8b-4161-8e76-6f461aaba42a@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Njq9SLglo7LSV5tU12g90qC4kLC3UrBc X-Proofpoint-ORIG-GUID: Njq9SLglo7LSV5tU12g90qC4kLC3UrBc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 adultscore=0 bulkscore=0 phishscore=0 mlxlogscore=949 spamscore=0 lowpriorityscore=0 clxscore=1015 mlxscore=0 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409240085 On 9/20/2024 6:14 PM, Krzysztof Kozlowski wrote: > On 20/09/2024 13:56, Sricharan Ramabadhran wrote: >> >>>> + >>>> +allOf: >>>> + - $ref: qcom,gcc.yaml# >>>> + >>>> +properties: >>>> + compatible: >>>> + const: qcom,ipq5424-gcc >>> >>> So everything i sthe same as 5332? Why not adding it there? >>> >> infact, ipq5332 has 1 dual lane and 1 single lane pcie, whereas >> ipq5424 has 2 dual lane and 2 single lane pcie. will update the >> bindings in v2 accordingly. > > Hm? What is the difference in the bindings? I don't see. Maybe some diff > would help. > For IPQ5424, clocks items is like this - description: Board XO clock source - description: Sleep clock source - description: PCIE 2lane PHY0 pipe clock source - description: PCIE 2lane PHY1 pipe clock source - description: PCIE 2lane PHY2 pipe clock source - description: PCIE 2lane PHY3 pipe clock source - description: USB PCIE wrapper pipe clock source For IPQ5332, its like this, - description: Board XO clock source - description: Sleep clock source - description: PCIE 2lane PHY pipe clock source - description: PCIE 2lane x1 PHY pipe clock source - description: USB PCIE wrapper pipe clock source So for IPQ5424, there are 2 additional PCI phy's. So would it be fine to add the new IPQ5424 compatible to IPQ5322 file itself with a 'if:' of compatibles ? Regards, Sricharan