Re: [PATCH v3 2/3] arm64: dts: qcom: x1e80100: Describe TLMM pins for SDC2

Abel Vesa
2024-11-05T11:01:42Z

On 24-11-04 15:06:29, Konrad Dybcio wrote:
> On 1.11.2024 12:21 PM, Abel Vesa wrote:
> > On 24-10-28 14:10:54, Konrad Dybcio wrote:
> >> On 28.10.2024 9:48 AM, Abel Vesa wrote:
> >>> On 24-10-25 20:34:19, Konrad Dybcio wrote:
> >>>> On 22.10.2024 12:46 PM, Abel Vesa wrote:
> >>>>> Describe the SDC2 default and sleep state pins configuration
> >>>>> in TLMM. Do this in SoC dtsi file since they will be shared
> >>>>> across multiple boards.
> >>>>>
> >>>>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> >>>>> ---
> >>>>
> >>>> Not very useful on its own but okay..
> >>>
> >>> Fair enough. For some reason, I'm not able to get sdc4 pinconf
> >>> to work.
> >>
> >> Any chance you tried to define 'sdc4_cmd' etc.? This one seems to have
> >> sdc4 pins on gpio127..=132
> >
> > Yes.
> >
> > But since the sdc4 pins can have other functions and since there is no
> > device that uses them (yet). Shouldn't we just skip describing the sdc4
> > pinconf entirely as that should be done on a per-board basis?
>
> By that argument, why describe the controller in the first place :|
>
> The possible pins are predefined and physically wired up inside the soc

Right, unlike the sdc2 ones, these can be muxed to a different function.

This is why I their pinconf need to be described in the board dts rather
than SoC dtsi. Since there is no board that supports it, we don't
describe them at all.

As for the controller, we should still describe it even if we don't have
ways to test it yet.

>
> Konrad