[PATCH v4 3/9] arm64: dts: amlogic: t7: Add MMC controller nodes

Ronald Claveau
2026-03-25T09:18:50Z

Add device tree nodes for the three MMC controllers available
on the Amlogic T7 SoC, using amlogic,meson-axg-mmc as fallback compatible.
All nodes are disabled by default and should be
enabled in the board-specific DTS file.

Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr>
---
arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 39 +++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
index 016b5429c8d1b..62c87d0ef7065 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
@@ -374,6 +374,45 @@ sec_ao: ao-secure@10220 {
reg = <0x0 0x10220 0x0 0x140>;
amlogic,has-chip-id;
};
+
+ sd_emmc_a: mmc@88000 {
+ compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc";
+ reg = <0x0 0x88000 0x0 0x800>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_A>,
+ <&clkc_periphs CLKID_SD_EMMC_A>,
+ <&scmi_clk CLKID_FCLK_DIV2>;
+ clock-names = "core", "clkin0", "clkin1";
+ assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_A_SEL>;
+ assigned-clock-parents = <&xtal>;
+ };
+
+ sd_emmc_b: mmc@8a000 {
+ compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc";
+ reg = <0x0 0x8a000 0x0 0x800>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_B>,
+ <&clkc_periphs CLKID_SD_EMMC_B>,
+ <&scmi_clk CLKID_FCLK_DIV2>;
+ clock-names = "core", "clkin0", "clkin1";
+ assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_B_SEL>;
+ assigned-clock-parents = <&xtal>;
+ };
+
+ sd_emmc_c: mmc@8c000 {
+ compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc";
+ reg = <0x0 0x8c000 0x0 0x800>;
+ interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_C>,
+ <&clkc_periphs CLKID_SD_EMMC_C>,
+ <&scmi_clk CLKID_FCLK_DIV2>;
+ clock-names = "core", "clkin0", "clkin1";
+ assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_C_SEL>;
+ assigned-clock-parents = <&xtal>;
+ };
};

};

--
2.49.0