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Tue, 20 May 2025 07:01:05 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 54K713FD020573 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 May 2025 07:01:04 GMT Received: from [10.218.0.120] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 20 May 2025 00:00:51 -0700 Message-ID: <3d867490-0738-4baf-9fd0-e522aa8d2677@quicinc.com> Date: Tue, 20 May 2025 12:30:51 +0530 Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V1 2/3] mmc: sdhci-msm: Enable tuning for SDR50 mode for SD card Content-Language: en-US To: Adrian Hunter , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bhupesh Sharma CC: , , , , , , , , , , , , , References: <20241107080505.29244-1-quic_sartgarg@quicinc.com> <20241107080505.29244-3-quic_sartgarg@quicinc.com> <4e4870b5-4491-4f65-9a41-1a5e9e1bdf68@intel.com> From: Sarthak Garg In-Reply-To: <4e4870b5-4491-4f65-9a41-1a5e9e1bdf68@intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 37qx-J20nTHUsPh0m709gGf2T0dyfiIX X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIwMDA1NiBTYWx0ZWRfX0U/EKY/m/vMB vVj87rvMt2ZQ6+2PtlY7/HF+JxmAn/8z0hDIVQ2VtbRsHddmW/HJM2SrmM6VNTNLTWtqz927Fk7 OoUbvEuQ+Nl3FZ1j3629KJloYvy/rxw+NIX7r4d1cxx2ny2ikFXxPOtwraHbffTVgdbGHghinIV ctOlGxPZr2bV5S+n6lAkLBVTgWGTw+1oTs1GZam+E5XoPFMXefT59ikD5t59wIePFXkdFhCzf+7 DP+PROMhVUcQuKyIlLgikERYgp7VLSS7JiLXTnb0axprMC+dRbiQ48uTaUymEBGR0DTs8DW6eTD EwojAV9TWPxGD2y66dhsJnnVMqY3RVbtZoq7Lu9ENqAfRhJ5BNeGqEorzpfA38UHm+MrciKElzN es++NoDH1iBOtpLm/1+YrkAMJDdNKAB7RUZD7SiV3wFIZBs1CVNmziD/2saQB2DCCJ83IfU8 X-Authority-Analysis: v=2.4 cv=K4giHzWI c=1 sm=1 tr=0 ts=682c28b1 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=05cVhv9CEcOWwgLMNlEA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: 37qx-J20nTHUsPh0m709gGf2T0dyfiIX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-20_03,2025-05-16_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 mlxlogscore=999 suspectscore=0 phishscore=0 clxscore=1011 malwarescore=0 lowpriorityscore=0 impostorscore=0 priorityscore=1501 mlxscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505200056 On 11/11/2024 2:21 PM, Adrian Hunter wrote: > On 7/11/24 10:05, Sarthak Garg wrote: >> For Qualcomm SoCs which needs level shifter for SD card, extra delay is >> seen on receiver data path. >> >> To compensate this delay enable tuning for SDR50 mode for targets which >> has level shifter. >> >> Signed-off-by: Sarthak Garg >> --- >> drivers/mmc/host/sdhci-msm.c | 16 ++++++++++++++++ >> 1 file changed, 16 insertions(+) >> >> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c >> index e00208535bd1..16325c21de52 100644 >> --- a/drivers/mmc/host/sdhci-msm.c >> +++ b/drivers/mmc/host/sdhci-msm.c >> @@ -81,6 +81,7 @@ >> #define CORE_IO_PAD_PWR_SWITCH_EN BIT(15) >> #define CORE_IO_PAD_PWR_SWITCH BIT(16) >> #define CORE_HC_SELECT_IN_EN BIT(18) >> +#define CORE_HC_SELECT_IN_SDR50 (4 << 19) >> #define CORE_HC_SELECT_IN_HS400 (6 << 19) >> #define CORE_HC_SELECT_IN_MASK (7 << 19) >> >> @@ -1124,6 +1125,10 @@ static bool sdhci_msm_is_tuning_needed(struct sdhci_host *host) >> { >> struct mmc_ios *ios = &host->mmc->ios; >> >> + if (ios->timing == MMC_TIMING_UHS_SDR50 && >> + host->flags & SDHCI_SDR50_NEEDS_TUNING) > > Please do line up code as suggested by checkpatch: > > CHECK: Alignment should match open parenthesis > #35: FILE: drivers/mmc/host/sdhci-msm.c:1129: > + if (ios->timing == MMC_TIMING_UHS_SDR50 && > + host->flags & SDHCI_SDR50_NEEDS_TUNING) > > CHECK: Alignment should match open parenthesis > #55: FILE: drivers/mmc/host/sdhci-msm.c:1219: > + if (ios.timing == MMC_TIMING_UHS_SDR50 && > + host->flags & SDHCI_SDR50_NEEDS_TUNING) { > > total: 0 errors, 0 warnings, 2 checks, 40 lines checked > > Sure will update in V2. >> + return true; >> + >> /* >> * Tuning is required for SDR104, HS200 and HS400 cards and >> * if clock frequency is greater than 100MHz in these modes. >> @@ -1192,6 +1197,8 @@ static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode) >> struct mmc_ios ios = host->mmc->ios; >> struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); >> struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); >> + const struct sdhci_msm_offset *msm_offset = msm_host->offset; >> + u32 config; >> >> if (!sdhci_msm_is_tuning_needed(host)) { >> msm_host->use_cdr = false; >> @@ -1208,6 +1215,15 @@ static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode) >> */ >> msm_host->tuning_done = 0; >> >> + if (ios.timing == MMC_TIMING_UHS_SDR50 && >> + host->flags & SDHCI_SDR50_NEEDS_TUNING) { > > Ditto alignment > Sure will update in V2. >> + config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); >> + config |= CORE_HC_SELECT_IN_EN; >> + config &= ~CORE_HC_SELECT_IN_MASK; >> + config |= CORE_HC_SELECT_IN_SDR50; > > Perhaps clear bits first, then set bits e.g. > > config &= ~CORE_HC_SELECT_IN_MASK; > config |= CORE_HC_SELECT_IN_EN | CORE_HC_SELECT_IN_SDR50; > Sure will update in V2. >> + writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); >> + } >> + >> /* >> * For HS400 tuning in HS200 timing requires: >> * - select MCLK/2 in VENDOR_SPEC >