From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64DAFC4167B for ; Mon, 12 Dec 2022 08:43:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231443AbiLLInW (ORCPT ); Mon, 12 Dec 2022 03:43:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53886 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231345AbiLLInV (ORCPT ); Mon, 12 Dec 2022 03:43:21 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4758E635C; Mon, 12 Dec 2022 00:43:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670834600; x=1702370600; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=fTnA3rhn0hS+bPRFffbtWjdNDZffwVX6s1BIs3HUKuQ=; b=PujLxoJ3RlGV14+Jj/IH2cNw4obz0rRn0l49U9Q/1C6+O9iGIZA40DNp od95WGfv5Xg+Ukd/Xru4FKZXz0PR+xls3g/uIwJUAXWadUS6srQVVAoh0 43QP5BS0E+x8P7iaxNf34aj53JbMPaw5PVRdERQ6CeCaOBudDjndK/hgq xrFLBjeptXwS4xGTPPGBZjHxgEgt0cm3uyysgAMze9w6Wnx1w7k9DwD8o M3VeaiMeMI9Gu1Msl0btfLmkfkA4eVaWAyqeApu+zHnHsu3aYgtJ0/N3x 5ds/coQ2DBdCmfDbzM3kADHDxcmnza+nPU0LvG0vTfqKDETq8hMqlobG2 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10558"; a="318944022" X-IronPort-AV: E=Sophos;i="5.96,237,1665471600"; d="scan'208";a="318944022" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2022 00:43:19 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10558"; a="772519076" X-IronPort-AV: E=Sophos;i="5.96,237,1665471600"; d="scan'208";a="772519076" Received: from ahunter6-mobl1.ger.corp.intel.com (HELO [10.0.2.15]) ([10.252.57.252]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2022 00:43:16 -0800 Message-ID: <44f642bc-8810-80d9-368a-15994de7f50d@intel.com> Date: Mon, 12 Dec 2022 10:42:36 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Firefox/102.0 Thunderbird/102.5.1 Subject: Re: [PATCH v3 3/3] mmc: xenon: Fix 2G limitation on AC5 SoC Content-Language: en-US To: Vadym Kochan , Hu Ziji , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Elad Nachman , Chris Packham References: <20221205105931.410686-1-vadym.kochan@plvision.eu> <20221205105931.410686-4-vadym.kochan@plvision.eu> <18cf4197-adce-3e47-7802-80b0d078368b@intel.com> <69dd8714-4be1-6b1b-fa07-04c790a6c6fc@intel.com> From: Adrian Hunter Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org On 9/12/22 15:27, Vadym Kochan wrote: > On Fri, 9 Dec 2022 14:13:06 +0200, Adrian Hunter wrote: >> On 9/12/22 14:10, Vadym Kochan wrote: >>> Hi Adrian, >>> >>> On Fri, 9 Dec 2022 13:53:58 +0200, Adrian Hunter wrote: >>>> On 9/12/22 13:39, Vadym Kochan wrote: >>>>> Hi Adrian, >>>>> >>>>> On Fri, 9 Dec 2022 09:23:05 +0200, Adrian Hunter wrote: >>>>>> On 5/12/22 12:59, Vadym Kochan wrote: >>>>>>> There is a limitation on AC5 SoC that mmc controller >>>>>>> can't have DMA access over 2G memory, so use SDMA with >>>>>>> a bounce buffer. Swiotlb can't help because on arm64 arch >>>>>>> it reserves memblock's at the end of the memory. >>>>>>> >>>>>>> Additionally set mask to 34 bit since on AC5 SoC RAM starts >>>>>>> at 0x2_00000000. >>>>>> >>>>>> Can you explain more about how a 34-bit DMA mask works when >>>>>> SDMA only supports 32-bit addresses? >>>>>> >>>>> >>>>> So, after I set >>>>> >>>>>>> + host->flags &= ~SDHCI_USE_64_BIT_DMA; >>>>> >>>>> then sdhc core sets mask to 32 bit, but then dma_map fails to map >>>>> bounce buffer because the base address is higher than 32bit - 0x2_00000000, >>>>> and 34bit mask fixed it. >>>> >>>> What happens if the bounce buffer gets mapped in the range >>>> 0x1_00000000 to 0x1_ffffffff ? >>>> >>> >>> From my understanding, on the AC5 SoC RAM starts at 0x2_00000000 so the bounce >>> buffer can be mapped in the range 0x2_00000000..0x2_ffffffff >> >> Right but I guess I meant what about 0x3_00000000..0x3_ffffffff ? >> Isn't that also in DMA_BIT_MASK(34) > > Yes, you are right. So it would fail in that case? Is it possible to use devicetree reserved memory or some such, to set aside 64k for the bounce buffer DMA mapping? > >> >>> >>>>> >>>>>>> >>>>>>> Co-developed-by: Elad Nachman >>>>>>> Signed-off-by: Elad Nachman >>>>>>> Signed-off-by: Vadym Kochan >>>>>>> --- >>>>>>> drivers/mmc/host/sdhci-xenon.c | 38 ++++++++++++++++++++++++++++++++++ >>>>>>> drivers/mmc/host/sdhci-xenon.h | 3 ++- >>>>>>> 2 files changed, 40 insertions(+), 1 deletion(-) >>>>>>> >>>>>>> diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c >>>>>>> index 08e838400b52..5f3db0425674 100644 >>>>>>> --- a/drivers/mmc/host/sdhci-xenon.c >>>>>>> +++ b/drivers/mmc/host/sdhci-xenon.c >>>>>>> @@ -13,7 +13,9 @@ >>>>>>> >>>>>>> #include >>>>>>> #include >>>>>>> +#include >>>>>>> #include >>>>>>> +#include >>>>>>> #include >>>>>>> #include >>>>>>> #include >>>>>>> @@ -253,6 +255,22 @@ static unsigned int xenon_get_max_clock(struct sdhci_host *host) >>>>>>> return pltfm_host->clock; >>>>>>> } >>>>>>> >>>>>>> +static int xenon_set_dma_mask(struct sdhci_host *host) >>>>>>> +{ >>>>>>> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); >>>>>>> + struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); >>>>>>> + struct mmc_host *mmc = host->mmc; >>>>>>> + struct device *dev = mmc_dev(mmc); >>>>>>> + >>>>>>> + if (priv->hw_version == XENON_AC5) { >>>>>>> + host->flags &= ~SDHCI_USE_64_BIT_DMA; >>>>>>> + >>>>>>> + return dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34)); >>>>>>> + } >>>>>>> + >>>>>>> + return sdhci_set_dma_mask(host); >>>>>>> +} >>>>>>> + >>>>>>> static const struct sdhci_ops sdhci_xenon_ops = { >>>>>>> .voltage_switch = xenon_voltage_switch, >>>>>>> .set_clock = sdhci_set_clock, >>>>>>> @@ -261,6 +279,7 @@ static const struct sdhci_ops sdhci_xenon_ops = { >>>>>>> .reset = xenon_reset, >>>>>>> .set_uhs_signaling = xenon_set_uhs_signaling, >>>>>>> .get_max_clock = xenon_get_max_clock, >>>>>>> + .set_dma_mask = xenon_set_dma_mask, >>>>>>> }; >>>>>>> >>>>>>> static const struct sdhci_pltfm_data sdhci_xenon_pdata = { >>>>>>> @@ -486,6 +505,18 @@ static void xenon_sdhc_unprepare(struct sdhci_host *host) >>>>>>> xenon_disable_sdhc(host, sdhc_id); >>>>>>> } >>>>>>> >>>>>>> +static int xenon_ac5_probe(struct sdhci_host *host) >>>>>>> +{ >>>>>>> + struct sysinfo si; >>>>>>> + >>>>>>> + si_meminfo(&si); >>>>>>> + >>>>>>> + if ((si.totalram * si.mem_unit) > SZ_2G) >>>>>>> + host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; >>>>>>> + >>>>>>> + return 0; >>>>>>> +} >>>>>>> + >>>>>>> static int xenon_probe(struct platform_device *pdev) >>>>>>> { >>>>>>> struct sdhci_pltfm_host *pltfm_host; >>>>>>> @@ -533,6 +564,12 @@ static int xenon_probe(struct platform_device *pdev) >>>>>>> } >>>>>>> } >>>>>>> >>>>>>> + if (priv->hw_version == XENON_AC5) { >>>>>>> + err = xenon_ac5_probe(host); >>>>>>> + if (err) >>>>>>> + goto err_clk_axi; >>>>>>> + } >>>>>>> + >>>>>>> err = mmc_of_parse(host->mmc); >>>>>>> if (err) >>>>>>> goto err_clk_axi; >>>>>>> @@ -682,6 +719,7 @@ static const struct of_device_id sdhci_xenon_dt_ids[] = { >>>>>>> { .compatible = "marvell,armada-ap807-sdhci", .data = (void *)XENON_AP807}, >>>>>>> { .compatible = "marvell,armada-cp110-sdhci", .data = (void *)XENON_CP110}, >>>>>>> { .compatible = "marvell,armada-3700-sdhci", .data = (void *)XENON_A3700}, >>>>>>> + { .compatible = "marvell,ac5-sdhci", .data = (void *)XENON_AC5}, >>>>>>> {} >>>>>>> }; >>>>>>> MODULE_DEVICE_TABLE(of, sdhci_xenon_dt_ids); >>>>>>> diff --git a/drivers/mmc/host/sdhci-xenon.h b/drivers/mmc/host/sdhci-xenon.h >>>>>>> index 3e9c6c908a79..0460d97aad26 100644 >>>>>>> --- a/drivers/mmc/host/sdhci-xenon.h >>>>>>> +++ b/drivers/mmc/host/sdhci-xenon.h >>>>>>> @@ -57,7 +57,8 @@ enum xenon_variant { >>>>>>> XENON_A3700, >>>>>>> XENON_AP806, >>>>>>> XENON_AP807, >>>>>>> - XENON_CP110 >>>>>>> + XENON_CP110, >>>>>>> + XENON_AC5 >>>>>>> }; >>>>>>> >>>>>>> struct xenon_priv { >>>>>> >>>>> >>>>> Regards, >>>> >>