From mboxrd@z Thu Jan 1 00:00:00 1970 From: Adrian Hunter Subject: Re: [PATCH v2] sdhci-esdhc-imx: Correct two register accesses Date: Tue, 11 Oct 2016 12:18:20 +0300 Message-ID: <4e944cda-05c6-0515-c98d-e90600f63541@intel.com> References: <1476124792-18441-1-git-send-email-aaron.brice@datasoft.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1476124792-18441-1-git-send-email-aaron.brice@datasoft.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Aaron Brice , ulf.hansson@linaro.org, aisheng.dong@nxp.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Dave Russell List-Id: linux-mmc@vger.kernel.org On 10/10/16 21:39, Aaron Brice wrote: > - The DMA error interrupt bit is in a different position as > compared to the sdhci standard. This is accounted for in > many cases, but not handled in the case of clearing the > INT_STATUS register by writing a 1 to that location. > - The HOST_CONTROL register is very different as compared to > the sdhci standard. This is accounted for in the write > case, but not when read back out (which it is in the sdhci > code). > > Signed-off-by: Dave Russell > Signed-off-by: Aaron Brice > Acked-by: Dong Aisheng Acked-by: Adrian Hunter