From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jaehoon Chung Subject: Re: [PATCH v2] mmc: dw_mmc: move rockchip related code to a separate file Date: Tue, 19 Aug 2014 14:08:02 +0900 Message-ID: <53F2DBB2.1000701@samsung.com> References: <1408003293-27375-1-git-send-email-addy.ke@rock-chips.com> <1408422974-22301-1-git-send-email-addy.ke@rock-chips.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-reply-to: <1408422974-22301-1-git-send-email-addy.ke@rock-chips.com> Sender: linux-doc-owner@vger.kernel.org To: Addy Ke , robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, rdunlap@infradead.org, tgih.jun@samsung.com, chris@printf.net, ulf.hansson@linaro.org, dinguyen@altera.com, heiko@sntech.de, olof@lixom.net, dianders@chromium.org Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, zhenfu.fang@rock-chips.com, cf@rock-chips.com, lintao@rock-chips.com, chenfen@rock-chips.com, zyf@rock-chips.com, xjq@rock-chips.com, huangtao@rock-chips.com, zyw@rock-chips.com, yzq@rock-chips.com, hj@rock-chips.com, kever.yang@rock-chips.com, zhangqing@rock-chips.com, hl@rock-chips.com List-Id: linux-mmc@vger.kernel.org Acked-by: Jaehoon Chung Best Regards, Jaehoon Chung On 08/19/2014 01:36 PM, Addy Ke wrote: > To support HS200 and UHS-1, we need add a big hunk of code, > as shown in the following patches. So a separate file for > rockchip SOCs is suitable. >=20 > Signed-off-by: Addy Ke > --- > Changes in v2: > - Kconfig: depend on ARCH_ROCKCHIP, suggested by Bartlomiej Zolnierki= ewicz > - Kconfig: depend on OF, suggested by Doug Anderson > - Not change suspend/resume code, suggested by Doug Anderson > - If pdev->dev.of_node is NULL, then return -ENODEV, suggested by Hei= ko St=C3=BCbner >=20 > drivers/mmc/host/Kconfig | 9 +++ > drivers/mmc/host/Makefile | 1 + > drivers/mmc/host/dw_mmc-pltfm.c | 57 ---------------- > drivers/mmc/host/dw_mmc-rockchip.c | 136 +++++++++++++++++++++++++++= ++++++++++ > 4 files changed, 146 insertions(+), 57 deletions(-) > create mode 100644 drivers/mmc/host/dw_mmc-rockchip.c >=20 > diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig > index a565254..f6095f6 100644 > --- a/drivers/mmc/host/Kconfig > +++ b/drivers/mmc/host/Kconfig > @@ -621,6 +621,15 @@ config MMC_DW_PCI > =20 > If unsure, say N. > =20 > +config MMC_DW_ROCKCHIP > + tristate "Rockchip specific extensions for Synopsys DW Memory Card = Interface" > + depends on MMC_DW && ARCH_ROCKCHIP && OF > + select MMC_DW_PLTFM > + help > + This selects support for Rockchip SoC specific extensions to the > + Synopsys DesignWare Memory Card Interface driver. Select this opt= ion > + for platforms based on RK3066, RK3188 and RK3288 SoC's. > + > config MMC_SH_MMCIF > tristate "SuperH Internal MMCIF support" > depends on MMC_BLOCK > diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile > index 7f81ddf..5fce465 100644 > --- a/drivers/mmc/host/Makefile > +++ b/drivers/mmc/host/Makefile > @@ -45,6 +45,7 @@ obj-$(CONFIG_MMC_DW_PLTFM) +=3D dw_mmc-pltfm.o > obj-$(CONFIG_MMC_DW_EXYNOS) +=3D dw_mmc-exynos.o > obj-$(CONFIG_MMC_DW_K3) +=3D dw_mmc-k3.o > obj-$(CONFIG_MMC_DW_PCI) +=3D dw_mmc-pci.o > +obj-$(CONFIG_MMC_DW_ROCKCHIP) +=3D dw_mmc-rockchip.o > obj-$(CONFIG_MMC_SH_MMCIF) +=3D sh_mmcif.o > obj-$(CONFIG_MMC_JZ4740) +=3D jz4740_mmc.o > obj-$(CONFIG_MMC_VUB300) +=3D vub300.o > diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mm= c-pltfm.c > index b547f7a..0c56c41 100644 > --- a/drivers/mmc/host/dw_mmc-pltfm.c > +++ b/drivers/mmc/host/dw_mmc-pltfm.c > @@ -26,64 +26,11 @@ > #include "dw_mmc.h" > #include "dw_mmc-pltfm.h" > =20 > -#define RK3288_CLKGEN_DIV 2 > - > static void dw_mci_pltfm_prepare_command(struct dw_mci *host, u32 *c= mdr) > { > *cmdr |=3D SDMMC_CMD_USE_HOLD_REG; > } > =20 > -static int dw_mci_rk3288_setup_clock(struct dw_mci *host) > -{ > - host->bus_hz /=3D RK3288_CLKGEN_DIV; > - > - return 0; > -} > - > -static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_io= s *ios) > -{ > - int ret; > - unsigned int cclkin; > - u32 bus_hz; > - > - /* > - * cclkin: source clock of mmc controller. > - * bus_hz: card interface clock generated by CLKGEN. > - * bus_hz =3D cclkin / RK3288_CLKGEN_DIV; > - * ios->clock =3D (div =3D=3D 0) ? bus_hz : (bus_hz / (2 * div)) > - * > - * Note: div can only be 0 or 1 > - * if DDR50 8bit mode(only emmc work in 8bit mode), > - * div must be set 1 > - */ > - if ((ios->bus_width =3D=3D MMC_BUS_WIDTH_8) && > - (ios->timing =3D=3D MMC_TIMING_MMC_DDR52)) > - cclkin =3D 2 * ios->clock * RK3288_CLKGEN_DIV; > - else > - cclkin =3D ios->clock * RK3288_CLKGEN_DIV; > - > - ret =3D clk_set_rate(host->ciu_clk, cclkin); > - if (ret) > - dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock); > - > - bus_hz =3D clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; > - if (bus_hz !=3D host->bus_hz) { > - host->bus_hz =3D bus_hz; > - /* force dw_mci_setup_bus() */ > - host->current_speed =3D 0; > - } > -} > - > -static const struct dw_mci_drv_data rk2928_drv_data =3D { > - .prepare_command =3D dw_mci_pltfm_prepare_command, > -}; > - > -static const struct dw_mci_drv_data rk3288_drv_data =3D { > - .prepare_command =3D dw_mci_pltfm_prepare_command, > - .set_ios =3D dw_mci_rk3288_set_ios, > - .setup_clock =3D dw_mci_rk3288_setup_clock, > -}; > - > static const struct dw_mci_drv_data socfpga_drv_data =3D { > .prepare_command =3D dw_mci_pltfm_prepare_command, > }; > @@ -144,10 +91,6 @@ EXPORT_SYMBOL_GPL(dw_mci_pltfm_pmops); > =20 > static const struct of_device_id dw_mci_pltfm_match[] =3D { > { .compatible =3D "snps,dw-mshc", }, > - { .compatible =3D "rockchip,rk2928-dw-mshc", > - .data =3D &rk2928_drv_data }, > - { .compatible =3D "rockchip,rk3288-dw-mshc", > - .data =3D &rk3288_drv_data }, > { .compatible =3D "altr,socfpga-dw-mshc", > .data =3D &socfpga_drv_data }, > {}, > diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw= _mmc-rockchip.c > new file mode 100644 > index 0000000..f0c2cb1 > --- /dev/null > +++ b/drivers/mmc/host/dw_mmc-rockchip.c > @@ -0,0 +1,136 @@ > +/* > + * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd > + * > + * This program is free software; you can redistribute it and/or mod= ify > + * it under the terms of the GNU General Public License as published= by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "dw_mmc.h" > +#include "dw_mmc-pltfm.h" > + > +#define RK3288_CLKGEN_DIV 2 > + > +static void dw_mci_rockchip_prepare_command(struct dw_mci *host, u32= *cmdr) > +{ > + *cmdr |=3D SDMMC_CMD_USE_HOLD_REG; > +} > + > +static int dw_mci_rk3288_setup_clock(struct dw_mci *host) > +{ > + host->bus_hz /=3D RK3288_CLKGEN_DIV; > + > + return 0; > +} > + > +static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_io= s *ios) > +{ > + int ret; > + unsigned int cclkin; > + u32 bus_hz; > + > + /* > + * cclkin: source clock of mmc controller > + * bus_hz: card interface clock generated by CLKGEN > + * bus_hz =3D cclkin / RK3288_CLKGEN_DIV > + * ios->clock =3D (div =3D=3D 0) ? bus_hz : (bus_hz / (2 * div)) > + * > + * Note: div can only be 0 or 1 > + * if DDR50 8bit mode(only emmc work in 8bit mode), > + * div must be set 1 > + */ > + if (ios->bus_width =3D=3D MMC_BUS_WIDTH_8 && > + ios->timing =3D=3D MMC_TIMING_MMC_DDR52) > + cclkin =3D 2 * ios->clock * RK3288_CLKGEN_DIV; > + else > + cclkin =3D ios->clock * RK3288_CLKGEN_DIV; > + > + ret =3D clk_set_rate(host->ciu_clk, cclkin); > + if (ret) > + dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock); > + > + bus_hz =3D clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; > + if (bus_hz !=3D host->bus_hz) { > + host->bus_hz =3D bus_hz; > + /* force dw_mci_setup_bus() */ > + host->current_speed =3D 0; > + } > +} > + > +static const struct dw_mci_drv_data rk2928_drv_data =3D { > + .prepare_command =3D dw_mci_rockchip_prepare_command, > +}; > + > +static const struct dw_mci_drv_data rk3288_drv_data =3D { > + .prepare_command =3D dw_mci_rockchip_prepare_command, > + .set_ios =3D dw_mci_rk3288_set_ios, > + .setup_clock =3D dw_mci_rk3288_setup_clock, > +}; > + > +static const struct of_device_id dw_mci_rockchip_match[] =3D { > + { .compatible =3D "rockchip,rk2928-dw-mshc", > + .data =3D &rk2928_drv_data }, > + { .compatible =3D "rockchip,rk3288-dw-mshc", > + .data =3D &rk3288_drv_data }, > + {}, > +}; > +MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match); > + > +static int dw_mci_rockchip_probe(struct platform_device *pdev) > +{ > + const struct dw_mci_drv_data *drv_data; > + const struct of_device_id *match; > + > + if (!pdev->dev.of_node) > + return -ENODEV; > + > + match =3D of_match_node(dw_mci_rockchip_match, pdev->dev.of_node); > + drv_data =3D match->data; > + > + return dw_mci_pltfm_register(pdev, drv_data); > +} > + > +#ifdef CONFIG_PM_SLEEP > +static int dw_mci_rockchip_suspend(struct device *dev) > +{ > + struct dw_mci *host =3D dev_get_drvdata(dev); > + > + return dw_mci_suspend(host); > +} > + > +static int dw_mci_rockchip_resume(struct device *dev) > +{ > + struct dw_mci *host =3D dev_get_drvdata(dev); > + > + return dw_mci_resume(host); > +} > +#endif /* CONFIG_PM_SLEEP */ > + > +static SIMPLE_DEV_PM_OPS(dw_mci_rockchip_pmops, > + dw_mci_rockchip_suspend, > + dw_mci_rockchip_resume); > + > +static struct platform_driver dw_mci_rockchip_pltfm_driver =3D { > + .probe =3D dw_mci_rockchip_probe, > + .remove =3D __exit_p(dw_mci_pltfm_remove), > + .driver =3D { > + .name =3D "dwmmc_rockchip", > + .of_match_table =3D dw_mci_rockchip_match, > + .pm =3D &dw_mci_rockchip_pmops, > + }, > +}; > + > +module_platform_driver(dw_mci_rockchip_pltfm_driver); > + > +MODULE_AUTHOR("Addy Ke "); > +MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension"); > +MODULE_ALIAS("platform:dwmmc-rockchip"); > +MODULE_LICENSE("GPL v2"); >=20